DETERMINING A LOCATION OF A MEMORY DEVICE IN A SOLID STATE DEVICE

• US 20160026564A1
• Filed: 10/01/2015
• Published: 01/28/2016
• Est. Priority Date: 10/13/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy
• Granted Patent: US 9,405,679 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/1048 Scalability
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A solid state device has a controller. The controller is configured to perform a first division operation that divides a received logical block address that indicates a physical memory block in a memory device of a plurality of memory devices in the solid state device by a number of logical block addresses per page of the physical memory block to obtain a result of the first division operation, configured to perform a second division operation that divides the obtained result of the first division operation by a number of memory devices in the plurality of memory devices, and configured to determine a location of the memory device of the plurality of memory devices within the solid state device from a location in a memory device table, the location in the memory device table identified by a remainder of the second division operation.

Claims

1. A solid state device comprising:

a controller;

wherein the controller is configured to perform a first division operation that divides a received logical block address that indicates a physical memory block in a memory device of a plurality of memory devices in the solid state device by a number of logical block addresses per page of the physical memory block to obtain a result of the first division operation;

wherein the controller is configured to perform a second division operation that divides the obtained result of the first division operation by a number of memory devices in the plurality of memory devices; and

wherein the controller is configured to determine a location of the memory device of the plurality of memory devices within the solid state device from a location in a memory device table, wherein the location in the memory device table is identified by a remainder of the second division operation.

2. The solid state device of claim 1, wherein the controller is configured to generate a data block look-up table.

3. The solid state device of claim 2, wherein the data block look-up table comprises an entry that comprises the received logical block address, wherein the entry points to the physical memory block indicated by the received logical block address.

4. The solid state device of claim 2, wherein the controller being configured to generate the data block look-up table comprises the controller being configured to generate the data block look-up table using a quotient of the of the second division operation and the remainder of the second division operation.

5. The solid state device of claim 4, wherein the controller being configured to generate the data block look-up table using the quotient of the of the second division operation and the remainder of the second division operation, comprises the controller being configured to calculate an index from the quotient of the second division operation and the remainder of the second division operation that points to the physical memory block indicated by the received logical block address.

6. The solid state device of claim 5, wherein the controller being configured to calculate the index from the quotient of the second division operation and the remainder of the second division operation comprises the controller being configured to perform a third division operation that divides the quotient of the second division operation by a number of pages in the physical memory block indicated by the received logical block address to produce a result of the third division operation, to perform a multiplication operation that multiplies the remainder of the second division operation by a number of memory blocks in the memory device of the plurality of memory devices to produce a result of the multiplication operation, and to add the result of the third division operation to the result of the multiplication operation to produce the index.

7. The solid state device of claim 3, wherein the entry indicates a highest programed page of the memory block indicated by the received logical block address.

8. The solid state device of claim 3, wherein the entry indicates an erased condition of the memory block indicated by the received logical block address.

9. The solid state device of claim 1, wherein the controller is configured to generate the memory device table.

10. The solid state device of claim 9, wherein the controller being configured to generate the memory device table comprises a Flash Translation Layer of the controller being configured to generate the memory device table.

11. The solid state device of claim 1, wherein the location in the memory device table comprises location characteristics of the memory device of the plurality of memory devices.

12. The solid state device of claim 1, wherein the received logical block address corresponds to a number of a page within the physical memory block and a position in that page.

13. A solid state device, comprising:

a controller;

wherein the controller is configured to determine the existence of parallel units within the solid state device;

wherein the controller is configured to generate a parallel unit look-up table that includes locations within the solid state device of the parallel units determined to exist within the solid state device;

wherein the controller is configured to determine a location within the solid state device of a target parallel unit that is determined to exist within the solid state device by determining an index for the target parallel unit and finding the location within the solid state device of the target parallel unit from a location in the parallel unit look-up table identified by the index for the target parallel unit, wherein the index for the target parallel unit is determined by dividing a logical block address indicating a memory block in the target parallel unit by a number of logical block addresses per page of the memory block to produce a first result and by performing a modulo operation dividing the first result by a number of memory devices in the parallel look up table to produce a second result, wherein the second result is the index for the target parallel unit.

14. A method of operating solid state device, the method comprising:

using a controller of the solid state device to perform a first division operation that divides a received logical block address that indicates a physical memory block in a memory device of a plurality of memory devices in the solid state device by a number of logical block addresses per page of the physical memory block to obtain a result of the first division operation;

using the controller to perform a second division operation that divides the obtained result of the first division operation by a number of memory devices in the plurality of memory devices, wherein a remainder of the second division operation identifies a location in a memory device table that specifies a location of the memory device of the plurality of memory devices within the solid state device; and

using the controller to determine the location of the memory device of the plurality of memory devices within the solid state device from the location in the memory device table.

15. The method of claim 14, further comprising using the controller to generate the memory device table.

16. The method of claim 15, wherein using the controller to generate the memory device table comprises using the controller to determine an existence of the plurality of memory devices within the solid state device and a location within the solid state device of each of the plurality of memory devices.

17. The method of claim 14, further comprising receiving the logical block address at a Flash Translation Layer of the controller from a host.

18. The method of claim 14, wherein the logical block address is a portion of a request that comprises a command.

19. The method of claim 14, further comprising using the controller to generate a data block look-up table comprising an entry that comprises the received logical block address, wherein the entry points to the physical memory block indicated by the received logical block address.

20. The method of claim 14, further comprising using the controller to perform a third division operation that divides a quotient of the second division operation by a number of pages in the physical memory block indicated by the received logical block address to produce a result of the third division operation, to perform a multiplication operation that multiplies the remainder of the second division operation by a number of memory blocks in the memory device of the plurality of memory devices to produce a result of the multiplication operation, and to add the result of the third division operation to the result of the multiplication operation to produce an index that points to the physical memory block indicated by the received logical block address.