NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD OF THE SAME

• US 20160027512A1
• Filed: 10/27/2014
• Published: 01/28/2016
• Est. Priority Date: 07/23/2014
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: HAGISHIMA, Daisuke, Nakamura, Mitsutoshi, Kondo, Shigeo, Hogyoku, Michiru
• Application Number:
  US14/524,046
• Publication Number:
  US 20160027512A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

A nonvolatile semiconductor memory device according to an embodiment includes a control unit, during the read sequence performed to an interested cell, performing a first read operation to detect that a threshold voltage of an adjacent cell is higher than a second reference voltage higher, performing a second read operation to detect that the threshold voltage of the interested cell is higher than a first reference voltage while applying a first bit line voltage to the adjacent bit line when threshold voltages of the adjacent cells are lower than the second reference voltage, and to detect that the threshold voltage of the interested cell is higher than the first reference voltage while applying a second bit line voltage higher than the first bit line voltage to the adjacent bit line when threshold voltages of the adjacent cells are higher than the second reference voltage, after the first read operation.

Claims

1. A nonvolatile semiconductor memory device comprising:

a memory cell array including a plurality of bit lines, a plurality of word lines and a source line that intersect the plurality of bit lines, and a plurality of memory strings that are provided between the bit line and the source line, each of the plurality of memory strings including a plurality of series-connected memory cells each of which is connected to the word line; and

a control unit that performs a write sequence writing data to the memory cell and a read sequence reading data from the memory cell, wherein,

assuming that the certain bit line is an interested bit line, that the bit line adjacent to the interested bit line is an adjacent bit line, that the certain memory cell belonging to the memory string between the interested bit line and the source line is an interested cell, and that the memory cell belonging to the memory string between the adjacent bit line and the source line and being commonly connected to the interested cell and the certain word line is an adjacent cell,

the control unit causes a threshold voltage of the memory cell to transition to a desired value higher than a first reference voltage after causing the threshold voltage to transition to a value lower than the first reference voltage during the write sequence,

the control unit, during the read sequence performed to the interested cell,

performs a first read operation to detect that the threshold voltage of the adjacent cell is higher than a second reference voltage higher than the first reference voltage,

performs a second read operation to detect that the threshold voltage of the interested cell is higher than the first reference voltage while applying a first bit line voltage to the adjacent bit line when threshold voltages of the adjacent cells are lower than the second reference voltage after the first read operation, and

performs the second read operation to detect that the threshold voltage of the interested cell is higher than the first reference voltage while applying a second bit line voltage higher than the first bit line voltage to the adjacent bit line when the threshold voltages of the adjacent cells are higher than the second reference voltage after the first read operation.

2. The nonvolatile semiconductor memory device according to claim 1, wherein the control unit applies the second bit line voltage to the adjacent bit line when the threshold voltage of one of the adjacent cells is higher than the second reference voltage during the second read operation.

3. The nonvolatile semiconductor memory device according to claim 1, wherein the control unit performs a third read operation to detect that the threshold voltage of the interested cell is higher than the first reference voltage and is lower than the second reference voltage during the read sequence performed to the interested cell.

4. The nonvolatile semiconductor memory device according to claim 2, wherein the control unit applies the first bit line voltage to the adjacent bit line irrespective of the threshold voltage of the adjacent cell during the third read operation.

5. The nonvolatile semiconductor memory device according to claim 2, wherein the control unit applies a voltage equal to a voltage which is applied to the adjacent bit line during the second read operation, to the adjacent bit line during the third read operation, when the third read operation is performed after the second read operation.

6. The nonvolatile semiconductor memory device according to claim 1, wherein

the memory cell stores a plurality of pieces of data using a plurality of threshold voltage distributions, and

the first reference voltage has a value between a lowest threshold voltage distribution and a threshold voltage distribution adjacent to the lowest threshold voltage distribution in the plurality of threshold voltage distributions.

7. The nonvolatile semiconductor memory device according to claim 1, wherein

the memory cell stores a plurality of pieces of data using a plurality of threshold voltage distributions, and

the second reference voltage has a value between a highest threshold voltage distribution and a threshold voltage distribution adjacent to the highest threshold voltage distribution in the plurality of threshold voltage distributions.

8. A nonvolatile semiconductor memory device comprising:

a memory cell array including a plurality of bit lines, a plurality of word lines and a source line that intersect the plurality of bit lines, and a plurality of memory strings that are provided between the bit line and the source line, each of the plurality of memory strings including a plurality of series-connected memory cells each of which is connected to the word line; and

a control unit that performs a write sequence writing data to the memory cell and a read sequence reading data from the memory cell, wherein,

assuming that the certain bit line is an interested bit line, that the bit line adjacent to the interested bit line is an adjacent bit line, that the certain memory cell belonging to the memory string between the interested bit line and the source line is an interested cell, and that the memory cell belonging to the memory string between the adjacent bit line and the source line and being commonly connected to the interested cell and the certain word line is an adjacent cell,

the memory cell stores first to fourth pieces of 2-bit data,

the control unit programs desired data after programming the first data in the memory cell during the write sequence,

the control unit, during the read sequence performed to the interested cell,

performs a first read operation to determine that storage data of the adjacent cell is the fourth data,

performs a second read operation to determine that storage data of the interested cell is the first data while applying a first bit line voltage to the adjacent bit line when both pieces of storage data of the adjacent cells are not the fourth data, and

performs the second read operation to determine that the storage data of the interested cell is the first data while applying a second bit line voltage higher than the first bit line voltage to the adjacent bit line when both the pieces of storage data of the adjacent cells are the fourth data.

9. The nonvolatile semiconductor memory device according to claim 8, wherein the control unit performs a third read operation to determine that the storage data of the interested cell is the third or fourth data during the read sequence performed to the interested cell.

10. The nonvolatile semiconductor memory device according to claim 8, wherein the control unit applies the first bit line voltage to the adjacent bit line irrespective of the storage data of the adjacent cell during the third read operation.

11. The nonvolatile semiconductor memory device according to claim 8, wherein the control unit applies a voltage equal to a voltage which is applied to the adjacent bit line during the second read operation, to the adjacent bit line during the third read operation, when the third read operation is performed after the second read operation.

12. The nonvolatile semiconductor memory device according to claim 8, wherein the memory cell stores the first to fourth pieces of data while associating the first to fourth pieces of data with sequentially-heightened first to fourth threshold voltage distributions.

13. The nonvolatile semiconductor memory device according to claim 8, wherein the first and second pieces of data differ from the third and fourth pieces of data in a first bit of the data, and the first and fourth pieces of data differ from the second and third pieces of data in a second bit of the data.

14. A method for operating a nonvolatile semiconductor memory device including:

a memory cell array including a plurality of bit lines, a plurality of word lines and a source line that intersect the plurality of bit lines, and a plurality of memory strings that are provided between the bit line and the source line, each of the plurality of memory strings including a plurality of series-connected memory cells each of which is connected to the word line; and

a control unit that performs a write sequence writing data in the memory cell and a read sequence reading data from the memory cell,

assuming that the certain bit line is an interested bit line, that the bit line adjacent to the interested bit line is an adjacent bit line, that the certain memory cell belonging to the memory string between the interested bit line and the source line is an interested cell, and that the memory cell belonging to the memory string between the adjacent bit line and the source line and being commonly connected to the interested cell and the certain word line is an adjacent cell,

the control unit causing a threshold voltage of the memory cell to transition to a desired value higher than a first reference voltage after causing the threshold voltage of the memory cell to transition to a value lower than the first reference voltage during the write sequence, wherein,

during the read sequence to the interested cell,

a first read operation to detect that the threshold voltage of the adjacent cell is higher than a second reference voltage higher than the first reference voltage is performed,

a second read operation to detect that the threshold voltage of the interested cell is higher than the first reference voltage is performed while a first bit line voltage is applied to the adjacent bit line when threshold voltages of the adjacent cells are lower than the second reference voltage after the first reference voltage, and

a second read operation to detect that the threshold voltage of the interested cell is higher than the first reference voltage is performed while a second bit line voltage higher than the first bit line voltage is applied to the adjacent bit line when threshold voltages of the adjacent cells are higher than the second reference voltage after the first reference voltage,

by the control unit.

15. The nonvolatile semiconductor memory device operation method according to claim 14, wherein the control unit applies the second bit line voltage to the adjacent bit line when the threshold voltage of one of the adjacent cells is higher than the second reference voltage during the second read operation.

16. The nonvolatile semiconductor memory device operation method according to claim 14, wherein the control unit performs a third read operation to detect that the threshold voltage of the interested cell is higher than the first reference voltage and is lower than the second reference voltage during the read sequence performed to the interested cell.

17. The nonvolatile semiconductor memory device operation method according to claim 15, wherein the control unit applies the first bit line voltage to the adjacent bit line irrespective of the threshold voltage of the adjacent cell during the third read operation.

18. The nonvolatile semiconductor memory device operation method according to claim 15, wherein the control unit applies a voltage equal to a voltage which is applied to the adjacent bit line during the second read operation, to the adjacent bit line during the third read operation, when the third read operation is performed after the second read operation.

19. The nonvolatile semiconductor memory device operation method according to claim 14, wherein

the memory cell stores a plurality of pieces of data using a plurality of threshold voltage distributions, and

the first reference voltage has a value between a lowest threshold voltage distribution and a threshold voltage distribution adjacent to the lowest threshold voltage distribution in the plurality of threshold voltage distributions.

20. The nonvolatile semiconductor memory device operation method according to claim 14, wherein

the memory cell stores a plurality of pieces of data using a plurality of threshold voltage distributions, and

the first reference voltage has a value between a highest threshold voltage distribution and a threshold voltage distribution adjacent to the highest threshold voltage distribution in the plurality of threshold voltage distributions.