METHOD FOR FORMING SEMICONDUCTOR STRUCTURE

• US 20160027699A1
• Filed: 08/18/2014
• Published: 01/28/2016
• Est. Priority Date: 07/23/2014
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chien, Chin-Cheng
• Granted Patent: US 9,312,180 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

The present invention provides a method for forming a semiconductor structure, including the following steps: Firstly, a substrate is provided, the substrate has a first region defined thereon, a plurality of fin structure is disposed within the first region, and an insulating layer is disposed on the substrate and between each fin structure; next, a first material layer is then formed on the insulating layer, and the fin structures is exposed simultaneously, afterwards, the fin structure is partially removed, and an epitaxial layer is then formed on the top surface of each remained fin structure.

Claims

1. A method for forming a semiconductor structure, at least comprising the following steps:

providing a substrate, a first region is defined on the substrate, and the first region comprises a plurality of fin structures, an insulating layer is disposed on the substrate and disposed between the fin structures;

forming a first material layer on the insulating layer, and parts of the fin structures are exposed simultaneously;

removing the fin structures partially;

removing the first material layer; and

forming an epitaxial layer on the top surface of each remained fin structure after the first material layer is removed.

2. The method of claim 1, wherein after the first material layer is formed, further comprising performing an etching back process to expose the top surface of each fin structure.

3. The method of claim 1, further comprising a second region, the second region comprising a plurality of fin structures, an insulating layer is disposed on the substrate and disposed between the fin structures.

4. The method of claim 3, further comprising forming a cap layer to cover the fin structures and the insulating layer within the first region and within the second region.

5. The method of claim 4, further comprising forming a second material layer on the cap layer.

6. The method of claim 5, further comprising removing the cap layer within the first region.

7. The method of claim 1, wherein after the fin structures are partially removed, further comprising removing the first material layer within the first region.

8. The method of claim 1, wherein after the fin structures are partially removed, the top surface of the fin structure is lower than the top surface of the insulating layer, and a trench is then defined by the first material layer, the insulating layer and the top surface of the fin structure.

9. The method of claim 8, wherein each epitaxial layer at least has a portion formed in the trench.

10. The method of claim 1, wherein every two adjacent epitaxial layers do not contact to each other.

11. The method of claim 1, wherein the first material layer still remains on the insulating layer while the fin structures are partially removed.