MOTHERBOARD, ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF, AND DISPLAY DEVICE

• US 20160027800A1
• Filed: 05/20/2014
• Published: 01/28/2016
• Est. Priority Date: 12/27/2013
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Chengdu BOE Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Chengdu BOE Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Inventors: LIU, Xu
• Granted Patent: US 9,461,074 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/1343 Electrodes reflective electrodes G02F1/133553
• CPC Class Codes: G02F 1/1345 Conductors connecting electrodes to cell terminals
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An array substrate and a fabrication method thereof, a display device including the array substrate and a motherboard including the array substrate are provided. The array substrate includes a pixel region and a peripheral wiring region. The peripheral wiring region includes a transparent conductive contact electrode disposed on a base substrate. The transparent conductive contact electrode is electrically connected with a metal electrode line disposed below the transparent conductive contact electrode through via holes disposed in different insulating layers, and the via holes disposed in different insulating layers do not overlap with each other in a projection direction.

Claims

1. An array substrate, comprising a pixel region and a peripheral wiring region, wherein,

the peripheral wiring region comprises a transparent conductive contact electrode disposed on a base substrate, the transparent conductive contact electrode is electrically connected with a metal electrode line disposed below the transparent conductive contact electrode through via holes disposed in different insulating layers, and the via holes disposed in different insulating layers do not overlap with each other in a projection direction.

2. The array substrate according to claim 1, wherein

the pixel region comprises a thin film transistor comprising a gate electrode, a source electrode and a drain electrode, a common electrode and a pixel electrode electrically connected with the drain electrode of the thin film transistor disposed on the base substrate;

and

the transparent conductive contact electrode is disposed in a same layer with either the pixel electrode or the common electrode which is provided above.

3. The array substrate according to claim 2, wherein

the pixel region further comprises a data line and a gate line disposed on the base substrate;

and

the metal electrode line comprises an extension line of the gate line and/or an extension line of the data line.

4. The array substrate according to claim 3, wherein

the thin film transistor is a thin film transistor of bottom gate type;

the extension line of the gate line is a gate line lead, and the gate line lead is disposed in a same layer with the gate line and the gate electrode of the thin film transistor;

the transparent conductive contact electrode is electrically connected with a source-drain electrode reserved pattern through a first via hole disposed in a passivation layer, and the source-drain electrode reserved pattern is electrically connected with the gate line lead through a second via hole disposed in a gate insulating layer;

the passivation layer is provided in the pixel region and the peripheral wiring region, the passivation layer is provided between the pixel electrode and the common electrode in the pixel region, and the source-drain electrode reserved pattern is disposed in a same layer with the source electrode and the drain electrode; and

the gate insulating layer is provided in the pixel region and the peripheral wiring region, the gate insulating layer is provided between the gate electrode and the source electrode as well as the drain electrode in the pixel region.

5. The array substrate according to claim 3, wherein

the thin film transistor is a thin film transistor of bottom gate type;

the extension line of the gate line is a gate line lead, and the gate line lead is disposed in a same layer with the gate line and the gate electrode of the thin film transistor;

the transparent conductive contact electrode is electrically connected with a first transparent electrode reserved pattern through a third via hole disposed in a passivation layer, and the first transparent electrode reserved pattern is electrically connected with the gate line lead through a fourth via hole disposed in a gate insulating layer;

the passivation layer is provided in the pixel region and the peripheral wiring region, the passivation layer is provided between the pixel electrode and the common electrode in the pixel region, and the first transparent electrode reserved pattern is disposed in a same layer with either the pixel electrode or the common electrode which is provided below; and

the gate insulating layer is provided in the pixel region and the peripheral wiring region, and the gate insulating layer is provided between the gate electrode and the source electrode as well as the drain electrode in the pixel region.

6. The array substrate according to claim 3, wherein

the thin film transistor is a thin film transistor of bottom gate type;

the extension line of the data line is a data line lead, and the data line lead is disposed in a same layer with the data line, and the source electrode and the drain electrode of the thin film transistor;

the transparent conductive contact electrode is electrically connected with a second transparent electrode reserved pattern through a fifth via hole disposed in a passivation layer, and the second transparent electrode reserved pattern is electrically connected with the data line lead through a sixth via hole disposed in a protective layer;

the passivation layer is provided in the pixel region and the peripheral wiring region, and the passivation layer is provided between the pixel electrode and the common electrode in the pixel region;

the second transparent electrode reserved pattern is disposed in a same layer with either the pixel electrode or the common electrode which is provided below; and

the protective layer is provided in the pixel region and the peripheral wiring region, and the protective layer is provided between the source electrode as well as the drain electrode and either the pixel electrode or the common electrode which is provided below.

7. The array substrate according to claim 3, wherein

the thin film transistor is a thin film transistor of top gate type;

the extension line of the data line is a data line lead, and the data line lead is disposed in a same layer with the data line, and the source electrode and the drain electrode of the thin film transistor;

the transparent conductive contact electrode is electrically connected with a gate electrode reserved pattern through a seventh via hole disposed in a passivation layer, and the gate electrode reserved pattern is electrically connected with the data line lead through an eighth via hole disposed in a gate insulating layer;

the passivation layer is provided in the pixel region and the peripheral wiring region, and the passivation layer is provided above the gate electrode in the pixel region;

the gate electrode reserved pattern is disposed in a same layer with the gate electrode; and

the gate insulating layer is provided in the pixel region and the peripheral wiring region, and the gate insulating layer is provided between the gate electrode and the source electrode as well as the drain electrode in the pixel region.

8. The array substrate according to claim 2, wherein

the transparent conductive contact electrode is disposed in a same layer with the common electrode;

and

the pixel electrode is disposed between the common electrode and the base substrate.

9. The array substrate according to claim 2, wherein

the transparent conductive contact electrode is disposed in a same layer with the pixel electrode;

and

the common electrode is disposed between the pixel electrode and the base substrate.

10. A fabrication method of an array substrate according to claim 1, comprising:

forming a metal electrode line and a transparent conductive contact electrode provided above the metal electrode line in a peripheral wiring region surrounding a pixel region of a base substrate,

wherein the transparent conductive contact electrode is electrically connected with the metal electrode line through via holes provided in different insulating layers, and the via holes provided in different insulating layers do not overlap with each other in a projection direction.

11. The fabrication method according to claim 10, wherein the fabrication method further comprises:

forming a thin film transistor comprising a gate electrode, a source electrode and a drain electrode, a common electrode and a pixel electrode electrically connected with the drain electrode of the thin film transistor in the pixel region of the base substrate;

wherein the transparent conductive contact electrode is formed in a same layer with either the pixel electrode or the common electrode which is provided above.

12. The fabrication method according to claim 11, wherein

the forming the metal electrode line in the peripheral wiring region of the base substrate comprises:

forming an extension line of a gate line and/or an extension line of a data line in the peripheral wiring region of the base substrate.

13. The fabrication method according to claim 12, wherein the fabrication method comprises:

forming a gate metal layer comprising the gate electrode and the gate line provided in the pixel region and a gate line lead provided in the peripheral wiring region on the base substrate, wherein the gate line lead is the extension line of the gate line;

forming a gate insulating layer provided in the pixel region and the peripheral wiring region and an active layer provided in the pixel region sequentially on the base substrate where the gate metal layer has been formed;

wherein a second via hole provided in the peripheral wiring region is formed in the gate insulating layer and the second via hole exposes the gate line lead;

forming a source-drain metal layer comprising the source electrode, the drain electrode and the data line electrically connected with the source electrode provided in the pixel region and a source-drain electrode reserved pattern provided in the peripheral wiring region on the base substrate where the gate insulating layer and the active layer have been formed;

wherein the source-drain electrode reserved pattern is electrically connected with the gate line lead through the second via hole;

forming a passivation layer on the base substrate where the source-drain metal layer has been formed;

wherein a first via hole provided in the peripheral wiring region is formed in the passivation layer and the first via hole exposes the source-drain electrode reserved pattern; and

forming a first transparent electrode provided in the pixel region and the transparent conductive contact electrode provided in the peripheral wiring region on the base substrate where the passivation layer has been formed, wherein the transparent conductive contact electrode is electrically connected with the source-drain electrode reserved pattern through the first via hole,

wherein before forming the passivation layer, the fabrication method further comprises;

forming a second transparent electrode provided in the pixel region on the base substrate;

one of the first transparent electrode and the second transparent electrode is the pixel electrode, and the other is the common electrode.

14. The fabrication method according to claim 12, wherein the fabrication method comprises:

forming a gate metal layer comprising the gate electrode and the gate line provided in the pixel region and a gate line lead provided in the peripheral wiring region on the base substrate, wherein the gate line lead is the extension line of the gate line;

forming a gate insulating layer provided in the pixel region and the peripheral region and an active layer provided in the pixel region sequentially on the base substrate where the gate metal layer has been formed;

wherein a fourth via hole provided in the peripheral wiring region is formed in the gate insulating layer, and the fourth via hole exposes the gate line lead;

forming a source-drain metal layer comprising the source electrode, the drain electrode and the data line electrically connected with the source electrode provided in the pixel region on the base substrate where the gate insulating layer and the active layer have been formed;

forming a first transparent electrode provided in the pixel region and a first transparent electrode reserved pattern provided in the peripheral wiring region on the base substrate where the source-drain metal layer has been formed;

wherein the first transparent electrode reserved pattern is electrically connected with the gate line lead through the fourth via hole;

forming a passivation layer on the base substrate where the first transparent electrode and the first transparent electrode reserved pattern have been formed;

wherein a third via hole provided in the peripheral wiring region is formed in the passivation layer, and the third via hole exposes the first transparent electrode reserved pattern; and

forming a second transparent electrode provided in the pixel region and the transparent conductive contact electrode provided in the peripheral wiring region on the base substrate where the passivation layer has been formed;

wherein the transparent conductive contact electrode is electrically connected with the first transparent electrode reserved pattern through the third via hole,

wherein one of the first transparent electrode and the second transparent electrode is the pixel electrode, and the other is the common electrode.

15. The fabrication method according to claim 12, wherein the fabrication method comprises:

forming a gate metal layer comprising the gate electrode and the gate line provided in the pixel region on the base substrate;

forming a gate insulating layer provided in the pixel region and the peripheral region and an active layer provided in the pixel region sequentially on the base substrate where the gate metal layer has been formed;

forming a source-drain metal layer comprising the source electrode, the drain electrode and the data line electrically connected with the source electrode provided in the pixel region and a data line lead provided in the peripheral wiring region on the base substrate where the gate insulating layer and the active layer have been formed, wherein the data line lead is the extension line of the data line;

forming a protective layer on the base substrate where the source-drain metal layer has been formed;

wherein a sixth via hole provided in the peripheral wiring region is formed in the protective layer, and the sixth via hole exposes the data line lead;

forming a second transparent electrode provided in the pixel region and a second transparent electrode reserved pattern provided in the peripheral wiring region on the base substrate where the protective layer has been formed;

forming a passivation layer on the base substrate where the second transparent electrode and the second transparent electrode reserved pattern have been formed;

wherein a fifth via hole provided in the peripheral wiring region is formed in the passivation layer, and the fifth via hole exposes the second transparent electrode reserved pattern;

forming a first transparent electrode provided in the pixel region and the transparent conductive contact electrode provided in the peripheral wiring region on the base substrate where the passivation layer has been formed, wherein the transparent conductive contact electrode is electrically connected with the second transparent electrode reserved pattern through the fifth via hole;

wherein one of the first transparent electrode and the second transparent electrode is the pixel electrode, and the other is the common electrode.

16. The fabrication method according to claim 2, wherein the fabrication method comprises:

forming a source-drain metal layer comprising the source electrode, the drain electrode and the data line connected with the source electrode provided in the pixel region and a data line lead provided in the peripheral wiring region on the base substrate, wherein the data line lead is the extension line of the data line;

forming an active layer provided in the pixel region and a gate insulating layer provided in the pixel region and the peripheral region sequentially on the base substrate where the source-drain metal layer has been formed;

wherein an eighth via hole provided in the peripheral wiring region is formed in the gate insulating layer, and the eighth via hole exposes the data line lead;

forming a gate metal layer comprising the gate electrode and the gate line provided in the pixel region and a gate electrode reserved pattern provided in the peripheral wiring region on the base substrate where the gate insulating layer has been formed;

forming a passivation layer on the base substrate where the gate metal layer has been formed;

wherein a seventh via hole provided in the peripheral wiring region is formed in the passivation layer, and the seventh via hole exposes the gate electrode reserved pattern;

forming a first transparent electrode provided in the pixel region and the transparent conductive contact electrode provided in the peripheral wiring region on the base substrate where the passivation layer has been formed, wherein the transparent conductive contact electrode is electrically connected with the gate electrode reserved pattern through the seventh via hole;

wherein before forming the passivation layer, the fabrication method further comprises;

forming a second transparent electrode provided in the pixel region on the base substrate; and

one of the first transparent electrode and the second transparent electrode is the pixel electrode, and the other is the common electrode.

18. A motherboard, comprising at least one array substrate, wherein the array substrate is an array substrate according to claim 1.

19. The motherboard according to claim 18, further comprising:

a test gate line in parallel with a data line of the array substrate, and electrically connected with a transparent conductive contact electrode; and

/or,

a test data line in parallel with a gate line of the array substrate, and electrically connected with the transparent conductive contact electrode;

wherein, the test gate line and/or the test data line are disposed in a same layer with the transparent conductive contact electrode.

20. The motherboard according to claim 19, wherein the test gate line and the test data line are electrically connected with each other.

17. (canceled)