ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY PANEL

• US 20160027801A1
• Filed: 08/15/2014
• Published: 01/28/2016
• Est. Priority Date: 02/19/2014
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectric Technology Co. Ltd. (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectric Technology Co. Ltd. (BOE Technology Group Co., Ltd.)
• Inventors: LIN, Lin, JIANG, Xuebing
• Granted Patent: US 9,947,691 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: H01L 21/77 Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate electrically programmable read-only memories or multistep manufacturing processes therefor H10B69/00
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/22 including, apart from doping materials or other impurities, only AIIBVI compounds
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

An array substrate, a manufacturing method thereof and a display panel are disclosed. The array substrate comprises: a base substrate (200) and gate lines (202), data lines (205) and a plurality of pixel units (20). Each pixel unit (20) includes a first thin-film transistor (TFT), a pixel electrode (208) and at least second TFT connected in series with the first TFT. The pixel electrode (208) is connected with a drain electrode (207′) of the second TFT; a source electrode (206′) of the second TFT is connected with a drain electrode (207) of the first TFT; and a source electrode (206) of the first TFT is connected with the data line (205). The array substrate can reduce the leakage current when the TFTs are switched off.

Claims

1. An array substrate comprising:

a base substrate and a gate line, a data line and a plurality of pixel units disposed on the base substrate, wherein

each pixel unit includes a first thin-film transistor (TFT), a pixel electrode and at least one second TFT connected in series with the first TFT; and

the pixel electrode is connected with a drain electrode of the second TFT;

a source electrode of the second TFT is connected with a drain electrode of the first TFT; and

a source electrode of the first TFT is connected with the data line.

2. The array substrate according to claim 1, wherein the first TFT and the second TFT are oxide TFTs or polycrystalline silicon (poly-Si) TFTs.

3. The array substrate according to claim 1, wherein

active layers of the first TFT and the second TFT are disposed on the base substrate;

the source electrode and the drain electrode of the first TFT and the source electrode and the drain electrode of the second TFT are respectively disposed on the active layers of the first TFT and the second TFT; and

the drain electrode of the second TFT is connected with the pixel electrode, extending to the drain electrode of the second TFT, in the pixel unit.

4. The array substrate according to any one of claim 1, wherein

the gate line is disposed on the base substrate;

a gate insulating layer and the active layers of the first TFT and the second TFT are disposed on the gate line;

an etching barrier layer is disposed on the gate insulating layer and the active layers of the first TFT and the second TFT;

the source electrode and the drain electrode of the first TFT and the source electrode and the drain electrode of the second TFT are disposed on the etching barrier layer;

a passivation layer is disposed on the source electrode and the drain electrode of the first TFT and the source electrode and the drain electrode of the second TFT; and

the drain electrode of the second TFT is connected with the pixel electrode, extending to the drain electrode of the second TFT, in the pixel unit.

5. The array substrate according to any one of claim 1, wherein

active layers of the first TFT and the second TFT are disposed on the base substrate;

an etching barrier layer is disposed on the active layers of the first TFT and the second TFT;

the source electrode and the drain electrode of the first TFT and the source electrode and the drain electrode of the second TFT are disposed on the etching barrier layer;

a gate insulating layer is disposed on the source electrode and the drain electrode of the first TFT and the source electrode and the drain electrode of the second TFT;

the gate line is disposed on the gate insulating layer;

a passivation layer is disposed on the gate line; and

the drain electrode of the second TFT is connected with the pixel electrode, extending to the drain electrode of the second TFT, in the pixel unit.

6. The array substrate according to any one of claim 1, wherein the array substrate is also provided with a common electrode and a common electrode line which are connected with each other.

7. The array substrate according to claim 6, wherein

the common electrode and the pixel electrode are arranged on different layers;

the pixel electrode or the common electrode disposed on a relatively upper layer includes a slit structure; and

the common electrode or the pixel electrode disposed on a relatively lower layer includes a slit structure or a plate structure;

or

the common electrode and the pixel electrode are arranged on the same layer; and

both the pixel electrode and the common electrode include a slit structure.

8. The array substrate according to claim 3, wherein the active layer is made from indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO) or poly-Si.

9. A display panel comprising the array substrate according to any one of claim 1.

10. A method for manufacturing an array substrate, comprising:

forming a gate line, a data line and a plurality of pixel units by patterning processes, in which each pixel unit includes a first TFT, a pixel electrode and at least one second TFT connected in series with the first TFT;

the pixel electrode is connected with a drain electrode of the second TFT;

a source electrode of the second TFT is connected with a drain electrode of the first TFT; and

a source electrode of the first TFT is connected with the data line.

11. The method according to claim 10, wherein the first TFT and the second TFT are oxide TFTs or poly-Si TFTs.

12. The method according to claim 10, wherein

forming patterns of an active layer of the first TFT and an active layer of the second TFT on the base substrate;

forming patterns of a source electrode and a drain electrode of the first TFT and a source electrode and a drain electrode of the second TFT on the base substrate provided with the patterns of the active layer of the first TFT and the active layer of the second TFT; and

forming patterns of the pixel electrode on the base substrate provided with the patterns of the source electrode and the drain electrode of the first TFT and the source electrode and the drain electrode of the second TFT, in which the pixel electrode is extended to and connected with the drain electrode of the second TFT.

13. The method according to claim 10, wherein

forming patterns of a gate line on the base substrate by a first patterning process;

forming patterns of a gate insulating layer, an active layer of the first TFT and an active layer of the second TFT on the base substrate, obtained after the first patterning process, by a second patterning process, in which the patterns of the active layers are disposed over the gate line;

forming a pattern of an etching barrier layer on the base substrate, obtained after the second patterning process, by a third patterning process;

forming patterns of a data line, a source electrode and a drain electrode of the first TFT and a source electrode and a drain electrode of the second TFT on the base substrate, obtained after the third patterning process, by a fourth patterning process;

forming a pattern of a passivation layer on the base substrate, obtained after the fourth patterning process, by a fifth patterning process; and

forming patterns of the pixel electrode on the base substrate, obtained after the fifth patterning process, by a sixth patterning process, in which the pixel electrode is extended to and connected with the drain electrode of the second TFT.

14. The method according to claim 10, wherein

forming patterns of an active layer of the first TFT and an active layer of the second TFT on the base substrate by a first patterning process;

forming a pattern of an etching barrier layer on the base substrate, obtained after the first patterning process, by a second patterning process;

forming patterns of a data line, a source electrode and a drain electrode of the first TFT and a source electrode and a drain electrode of the second TFT on the base substrate, obtained after the second patterning process, by a third patterning process;

forming patterns of a gate insulating layer and a gate line on the base substrate, obtained after the third patterning process, by a fourth patterning process, in which the a pattern of the gate line is disposed over the active layers;

forming a pattern of a passivation layer on the base substrate, obtained after the fourth patterning process, by a fifth patterning process; and

forming patterns of the pixel electrode on the base substrate, obtained after the fifth patterning process, by a sixth patterning process, in which the pixel electrode is extended to and connected with the drain electrode of the second TFT.

15. The method according to claim 13, in the same patterning process of forming the patterns of the gate lines, further comprising:

forming a common electrode line and the gate line at the same time.