DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME

• US 20160027808A1
• Filed: 05/20/2015
• Published: 01/28/2016
• Est. Priority Date: 07/25/2014
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: KIM, DUK-SUNG
• Granted Patent: US 9,698,168 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]

Abstract

An array substrate for a display device includes a first base substrate; a thin film transistor disposed on the first base substrate that includes a semiconductor layer, a gate electrode, a source electrode, and a drain electrode; a first passivation layer that covers the thin film transistor and that includes an inorganic insulating material; a second passivation layer disposed on the first passivation layer that includes an exposure hole that exposes the first passivation layer on the drain electrode; a common electrode disposed on the second passivation layer; a third passivation layer that covers the common electrode and that includes a contact hole inside the exposure hole to expose the drain electrode; a cavity between the first passivation layer and the third passivation layer on the drain electrode; and a pixel electrode disposed on the third passivation layer and connected with the drain electrode.

Claims

1. A display device, comprising:

a first base substrate;

a thin film transistor disposed on the first base substrate that includes a semiconductor layer, a gate electrode, a source electrode, and a drain electrode;

a first passivation layer that covers the thin film transistor and that includes an inorganic insulating material;

a second passivation layer disposed on the first passivation layer that includes an exposure hole exposing the first passivation layer on the drain electrode;

a common electrode disposed on the second passivation layer;

a third passivation layer that covers the common electrode and that includes a contact hole disposed inside the exposure hole exposing the drain electrode;

a cavity between the first passivation layer and the third passivation layer on the drain electrode; and

a pixel electrode disposed on the third passivation layer and connected with the drain electrode.

2. The display device of claim 1, wherein the first passivation layer includes a silicon nitride layer and a silicon oxide layer disposed on the silicon nitride layer.

3. The display device of claim 1, wherein the second passivation layer includes a photosensitive organic insulating material.

4. The display device of claim 1, wherein an internal lateral surface of the exposure hole is inclined.

5. The display device of claim 4, wherein the common electrode extends into the internal lateral surface of the exposure hole.

6. The display device of claim 1, wherein the cavity separates the common electrode and the pixel electrode and a distance in the cavity between the common electrode and the pixel electrode is from about 0.5 μ

m to about 1 μ

m.

7. The display device of claim 1, wherein the semiconductor layer includes an oxide semiconductor.

8. The display device of claim 1, further comprising:

a gate line on the first base substrate;

a data line on the base substrate that crosses the gate line, wherein the gate electrode protrudes from the gate line, and the source electrode protrudes from the data line;

a common voltage line that includes a same material as that of the gate line, the common voltage line being parallel to the gate line and crossing the data line; and

a contact pad that electrically connects the common voltage line to the common electrode.

9. The display device of claim 1, further comprising:

an opposite substrate facing the array substrate; and

a liquid crystal layer between the array substrate and the opposite substrate,

wherein the opposite substrate includes;

a second base substrate;

a black matrix disposed on a surface of the second base substrate facing the array substrate; and

an overcoat layer that covers the black matrix.

10. A method of fabricating a display device, comprising:

forming a thin film transistor on a first base substrate;

forming a first passivation layer on the first base substrate that covers the thin film transistor, wherein the first passivation layer includes an inorganic insulating material;

forming a second passivation layer on the first passivation layer;

patterning the second passivation layer to form an exposure hole that exposes the first passivation layer on a drain electrode of the thin film transistor;

forming a common electrode on the second passivation layer, wherein the common electrode includes a transparent conductive oxide;

forming a third passivation layer on the common electrode;

patterning the third passivation layer to expose the common electrode on the drain electrode

etching the common electrode to form a cavity between the first passivation layer and the third passivation layer on the drain electrode;

patterning the first passivation layer to expose the drain electrode; and

forming a pixel electrode connected to the drain electrode on the third passivation layer.

11. The method of claim 10, wherein the second passivation layer includes a photosensitive organic insulating material, and the second passivation layer is patterned by an exposure process, wherein an intensity of ultraviolet light irradiated to a center part of an exposed region of the second passivation layer may differ from an intensity of the ultraviolet light irradiated to an edge part of the exposed region of the second passivation layer.

12. The method of claim 11, wherein an internal lateral surface of the exposure hole is inclined, and the common electrode extends into the internal lateral surface of the exposure hole.

13. The method of claim 10, wherein the common electrode and the pixel electrode are spaced apart from each other by the cavity and a distance in the cavity between the common electrode and the pixel electrode is from about 0.5 μ

m to about 1 μ

m.

14. The method of claim 12, further comprising:

forming a gate line and a data line on the first base substrate; and

forming a common voltage line together with the gate line that is parallel to the gate line.

15. The method of claim 14, wherein the patterning of the third passivation layer exposes a part of the common electrode on the drain electrode and on the common voltage line, wherein the exposed region of the common electrode is etched to the internal lateral surface of the exposure hole by adjusting a duration of a wet etching process.

16. The method of claim 15, wherein the first passivation layer includes a silicon nitride layer and a silicon oxide layer disposed on the silicon nitride layer,

wherein patterning the first passivation layer forms a first contact hole that exposes the drain electrode, and a second contact hole that exposes the common voltage line, and a duration of an etching process that forms the second contact hole is longer than a duration of the etching process that forms the first contact hole, and

the third passivation layer is partially etched on the common voltage line while the second contact hole is being formed, to expose part of the common electrode.

17. The method of claim 16, further comprising:

forming a contact pad together with the pixel electrode that electrically connects the common voltage line and the common electrode.

18. An array substrate, comprising:

a thin film transistor disposed on a first base substrate;

a first passivation layer that covers the thin film transistor;

a second passivation layer disposed on the first passivation layer that includes an exposure hole with an inclined internal lateral surface that exposes the first passivation layer on a drain electrode of the thin film transistor;

a common electrode disposed on the second passivation layer that extends into the internal lateral surface of the exposure hole;

a third passivation layer that covers the common electrode and that includes a contact hole disposed inside the exposure hole exposing the drain electrode;

a cavity between the first passivation layer and the third passivation layer on the drain electrode; and

a pixel electrode disposed on the third passivation layer and connected with the drain electrode, wherein the cavity separates the common electrode and the pixel electrode.

19. The array substrate of claim 18, wherein a distance in the cavity between the common electrode and the pixel electrode is from about 0.5 μ

m to about 1 μ

m.

20. The array substrate of claim 18, further comprising:

a gate line on the first base substrate;

a data line on the base substrate that crosses the gate line;

a common voltage line that includes a same material as that of the gate line, the common voltage line being parallel to the gate line and crossing the data line; and

a contact pad that electrically connects the common voltage line to the common electrode,

wherein the thin film transistor further includes a gate electrode protruding from the gate line, a source electrode protruding from the data line, and a semiconductor layer.