ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY DEVICE
First Claim
1. A manufacturing method of an array substrate, comprising:
- forming a pattern layer including a pixel electrode and a pattern layer including a gate electrode and a gate line on a base substrate through one patterning process;
on the substrate with the pattern layer including the gate electrode and the gate line formed thereon, through one patterning process or two patterning processes, forming a gate insulating layer, a pattern layer at least including a metal oxide semiconductor active layer and a pattern layer at least including an etch stop layer;
wherein, a first via hole for exposing the pixel electrode is formed over the pixel electrode;
on the substrate with the etch stop layer formed thereon, through one patterning process, forming a pattern layer including a source electrode, a drain electrode and a data line;
wherein, the source electrode and the drain electrode each contact with the metal oxide semiconductor active layer, and the drain electrode and the pixel electrode are electrically connected through the first via hole.
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Accused Products
Abstract
A manufacturing method of an array substrate, including: forming a pattern layer including a pixel electrode, and a pattern layer including a gate electrode and a gate line on a base substrate; on the substrate with the pattern layer including the gate electrode and the gate line formed thereon, forming a gate insulating layer, a pattern layer at least including a metal oxide semiconductor active layer and a pattern layer at least including an etch stop layer; wherein, a first via hole for exposing the pixel electrode is formed over the pixel electrode; on the substrate with the etch stop layer formed thereon, forming a pattern layer including a source electrode, a drain electrode and a data line; wherein, the source electrode and the drain electrode each contact a metal oxide semiconductor active layer, and the drain electrode is electrically connected to the pixel electrode through the first via hole.
12 Citations
20 Claims
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1. A manufacturing method of an array substrate, comprising:
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forming a pattern layer including a pixel electrode and a pattern layer including a gate electrode and a gate line on a base substrate through one patterning process; on the substrate with the pattern layer including the gate electrode and the gate line formed thereon, through one patterning process or two patterning processes, forming a gate insulating layer, a pattern layer at least including a metal oxide semiconductor active layer and a pattern layer at least including an etch stop layer;
wherein, a first via hole for exposing the pixel electrode is formed over the pixel electrode;on the substrate with the etch stop layer formed thereon, through one patterning process, forming a pattern layer including a source electrode, a drain electrode and a data line;
wherein, the source electrode and the drain electrode each contact with the metal oxide semiconductor active layer, and the drain electrode and the pixel electrode are electrically connected through the first via hole. - View Dependent Claims (2, 3, 4, 5, 6, 7, 14)
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8. An array substrate, comprising:
- a pattern layer including a gate electrode and a gate line, a gate insulating layer, a metal oxide semiconductor active layer, a pixel electrode, and a pattern layer including a source electrode, a drain electrode and a data line;
wherein, the array substrate further includes;a transparent conductive pattern layer disposed under the pattern layer including the gate electrode and the gate line, the transparent conductive pattern lying in the same layer as the pixel electrode; an etch stop layer disposed over the metal oxide semiconductor active layer;
wherein, the source electrode and the drain electrode are located over the etch stop layer, and the drain electrode is electrically connected to the pixel electrode through a first via hole located over the pixel electrode. - View Dependent Claims (9, 10, 12, 13, 15, 16, 17, 18, 19, 20)
- a pattern layer including a gate electrode and a gate line, a gate insulating layer, a metal oxide semiconductor active layer, a pixel electrode, and a pattern layer including a source electrode, a drain electrode and a data line;
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11. The array substrate according to claim wherein, the first via hole is joined to the third via hole.
Specification