SEMICONDUCTOR DEVICES AND STRUCTURES
First Claim
1. A semiconductor device structure, comprising:
- a plurality of features extending from a substrate, neighboring features of the plurality spaced from one another by a trench exposing a portion of the substrate, at least one feature of the plurality comprising;
a region of at least one conductive material over the substrate; and
a liner on sidewalk of the region of the at least one conductive material.
7 Assignments
0 Petitions
Accused Products
Abstract
Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control gate region.
13 Citations
20 Claims
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1. A semiconductor device structure, comprising:
a plurality of features extending from a substrate, neighboring features of the plurality spaced from one another by a trench exposing a portion of the substrate, at least one feature of the plurality comprising; a region of at least one conductive material over the substrate; and a liner on sidewalk of the region of the at least one conductive material. - View Dependent Claims (2, 3, 14, 15, 16, 17)
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4. A semiconductor device, comprising:
a plurality of memory cells, at least one memory cell of the plurality comprising; a control gate region comprising a metallic material; a capping region overlying the control gate region, sidewalk of the control gate region substantially aligning with sidewalk of the capping region; and a charge structure under the control gate region. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11, 12, 13)
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18. A semiconductor device comprising an array of memory cell structures, a memory cell structure of the array of memory cell structures comprising:
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a control gate region electrically isolated from an underlying charge structure by a region of a dielectric material; another region of another dielectric material underlying the charge structure and overlying a substrate; and a capping region over the control gate region, the memory cell structure defining a tapering width along a sidewall of the memory cell from the substrate toward the region of dielectric material underlying the control gate region, and the memory cell structure defining a substantially consistent width along the sidewall of the memory cell from the control gate region to an upper surface of the capping region. - View Dependent Claims (19, 20)
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Specification