Vertical Tunneling Field-Effect Transistor Cell and Fabricating the Same

• US 20160027898A1
• Filed: 10/03/2015
• Published: 01/28/2016
• Est. Priority Date: 01/18/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chuang, Harry-Hak-Lay, Kuo, Cheng-Cheng, Zhu, Ming
• Granted Patent: US 9,806,172 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/66356 Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7391 Gated diode structures
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A tunneling field-effect transistor (TFET) device is disclosed. A protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the protrusion structure and extends to a bottom portion of the protrusion structure as a raised drain region. A drain contact is disposed over the drain region and overlap with the isolation feature.

Claims

1. A method for forming a field effect transistor (FET), the method comprising:

providing a substrate;

etching the substrate to form a protrusion on a surface of the substrate;

forming isolation features on the substrate;

doping a portion of the substrate adjacent to the protrusion to form a drain region between the isolation features, including doping a lower portion of the protrusion to form a raised drain region;

forming a first isolation dielectric layer over the drain region;

forming a gate stack having a planar portion over the drain region, which is parallel to the surface of the substrate and has a sidewall and a gating surface, which wraps around a middle portion of the protrusion and which overlaps with the raised drain region;

forming a second isolation dielectric layer over the planar portion of the gate stack and the raised drain region;

recessing a portion of the gating surface of the gate stack to expose a top portion of the protrusion;

forming a source region on the top portion of the protrusion with a different doping type than the drain region, the source region overlapping with the gating surface of the gate stack;

forming a third isolation dielectric layer over the source region, the gate stack and the second isolation dielectric layer;

forming a drain contact on the drain region and a portion of one of the isolation features together; and

simultaneously with the drain contact formation, forming a gate contact on the planar portion of the gate stack and the sidewall of the planar portion of the gate stack, the gate contact extending through a portion of the isolation dielectric layer, and forming a source contact on the source region.

2. The method of claim 1, wherein the portion of the one of the isolation features is removed to expose a portion of the drain region in the drain contact.

3. The method of claim 1, further comprising forming the middle portion of the protrusion out of the same material as the substrate.

4. The method of claim 1, wherein the protrusion structure is formed as a cylinder.

5. The method of claim 1, wherein the protrusion structure is formed as one of a square-column structure and a hexagonal-column structure.

6. The method of claim 1, wherein the protrusion structure is formed as an oval-cylinder structure.

7. The method of claim 1, wherein forming the gate stack includes forming the gate stack from a high-k/metal material.

8. A method for forming a field effect transistor (FET), the method comprising:

providing a substrate having a protrusion structure formed on a planar surface of the substrate, the protrusion structure having a top portion, a middle portion, and a bottom portion;

forming an isolation structure in the substrate;

forming a drain region in the substrate and in the bottom portion of the protrusion structure;

forming a gate structure over the drain region and on a sidewall of the protrusion structure, the gate structure surrounding the protrusion structure and having a planar region extending away from the protrusion structure and having a sidewall;

forming a source region in the top portion of the protrusion structure;

forming a drain contact landing on a portion of the drain region and on a portion of the isolation structure;

forming a gate contact landing on a portion of the planar region of the gate structure and on a portion of the sidewall of the planar region of the gate structure; and

forming a source contact landing on the source region.

9. The method of claim 8, wherein the gate structure includes a dielectric layer, a high-k gate dielectric, and a metal gate layer.

10. The method of claim 8, further comprising forming an isolation dielectric layer over the drain region.

11. The method of claim 10, wherein the isolation dielectric layer is a first isolation dielectric layer that is formed beneath the gate structure, the method further comprising:

forming a second isolation dielectric layer over the planar region of the gate structure and beneath a top surface of the gate structure; and

forming a third isolation dielectric layer over the second isolation dielectric layer and over the gate structure.

12. The method of claim 8, further comprising removing the portion of the drain region so that the drain contact landing on the portion of the drain region is in contact with a sidewall of the drain region.

13. The method of claim 8, wherein the middle portion of the protrusion structure is comprised of the same material as the substrate.

14. The method of claim 8, wherein the protrusion structure is formed as a cylinder.

15. A method for forming a field effect transistor (FET), the method comprising:

receiving a substrate, the substrate having a protrusion formed thereon;

forming an isolation structure in the substrate, the isolation structure surrounding the protrusion;

forming a drain feature in the substrate, the drain feature extending into a bottom portion of the protrusion;

forming a source feature in a top portion of the protrusion;

forming a gate feature on a sidewall of the protrusion such that the gate feature is in contact with the top portion of the protrusion and the bottom portion of the protrusion, the gate feature having a planar portion extending laterally away from the protrusion parallel to the drain region and having a sidewall;

forming a source contact on the source region;

forming a drain contact on the drain region and overlapping with the isolation structure; and

forming a gate contact on the planar portion of the gate feature and in contact with the sidewall of the gate feature.

16. The method of claim 15, further comprising:

forming a first isolation dielectric layer over the drain region such that the gate feature is vertically separated from the drain region by the first isolation dielectric layer; and

forming a second isolation dielectric layer over the gate feature.

17. The method of claim 16, wherein the second isolation dielectric layer is in contact with the sidewall of the planar portion of the gate feature.

18. The method of claim 15, wherein the protrusion has a middle portion comprised of the same material as the substrate.

19. The method of claim 15, further comprising removing a portion of the isolation structure that is overlapped by the drain contact such that a portion of the drain contact overlapping with the isolation structure is in contact with the drain region.

20. The method of claim 15, wherein the gate contact and the drain contact are formed on opposite sides of the protrusion structure.