LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME

• US 20160027982A1
• Filed: 10/05/2015
• Published: 01/28/2016
• Est. Priority Date: 12/12/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: SUGIZAKI, Yoshiaki, KOJIMA, Akihiro, SHIBATA, Hideki, ISHIKAWA, Masayuki, TAMURA, Hideo, KOMATSU, Tetsuro
• Granted Patent: US 9,478,722 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/02375 Top view
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05012 in top view
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05555 being circular or elliptic
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06132 being non uniform, i.e. having a non uniform pitch across the array
• CPC Class Codes: H01L 2224/06152 being non uniform, i.e. having a non uniform pitch across the array
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13599 Material
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/29599 Material
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 25/0753 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2933/0016 : relating to electrodes
• CPC Class Codes: H01L 2933/0033 : relating to semiconductor body packages
• CPC Class Codes: H01L 2933/0041 : relating to wavelength conversion elements
• CPC Class Codes: H01L 2933/0066 : relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/0093 : Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/34 : containing only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 33/38 : with a particular shape
• CPC Class Codes: H01L 33/44 : characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/486 : adapted for surface mounting
• CPC Class Codes: H01L 33/50 : Wavelength conversion elements
• CPC Class Codes: H01L 33/58 : Optical field-shaping elements
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

A method for manufacturing a light emitting device includes forming a multilayer body including a light emitting layer so that a first surface thereof is adjacent to a first surface side of a translucent substrate. A dielectric film on a second surface side opposite to the first surface of the multilayer body is formed having first and second openings on a p-side electrode and an n-side electrode. A seed metal on the dielectric film and an exposed surface of the first and second openings form a p-side metal interconnect layer and an n-side metal interconnect layer separating the seed metal into a p-side seed metal and an n-side seed metal by removing a part of the seed metal. A resin is formed in a space from which the seed metal is removed.

Claims

1. (canceled)

2. A method for manufacturing a light emitting device comprising:

bonding end portions of first and second extraction electrodes of a semiconductor light emitting device to a mounting member,

the semiconductor light emitting device includes

a multilayer having a first surface and a second surface opposite to the first surface, and including a light emitting layer, the multilayer not including a substrate on the first surface side,

a first electrode provided on the multilayer,

a second electrode provided on the second surface of a stacked part including the light emitting layer of the multilayer,

a first insulating film having openings conducting to the first electrode and the second electrode,

a first metal interconnect layer connected to the first electrode,

a second metal interconnect layer connected to the second electrode,

the first extraction electrode provided on the second surface side and connected to the first metal interconnect layer, the first extraction electrode thicker than the multilayer, the end portion of the first extraction electrode not being bonded to a mounting member,

the second extraction electrode provided on the second surface side and connected to the second metal interconnect layer, the second extraction electrode thicker than the multilayer, the end portion of the second extraction electrode not being bonded to a mounting member,

a second insulating film provided between the first extraction electrode and the second extraction electrode, and thicker than the multilayer, and

a layer provided on the first surface side of the multilayer without a substrate between the multilayer and the layer, the layer containing at least one of a phosphor and a resin,

a part of the first metal interconnect layer facing to a part of the second surface of the stacked part including the light emitting layer of the multilayer with interposing the first insulating film between the part of the first metal interconnect layer and the part of the second surface of the stacked part of the multilayer.

3. The method according to claim 2, wherein

a plurality of multilayers are formed on a substrate, and then the substrate is removed from the multilayer with not bonding the end portion of the first extraction electrode and the end portion of the second extraction electrode to the mounting member,

the layer containing at least one of the phosphor and the resin is formed on the first surface from which the substrate had been removed.

4. The method according to claim 3, wherein

after forming the layer containing at least one of the phosphor and the resin, a wafer including the plurality of multilayer is singulated.

5. The method according to claim 2, wherein

a contact area between the first metal interconnect layer and the first extraction electrode is larger than a contact area between the first electrode and the first metal interconnect layer.

6. The method according to claim 2, wherein

the multilayer has a side surface continued from the first surface,

the first insulating film is provided on an outside of the side surface of the multilayer, and

the layer containing at least one of the phosphor and the resin is provided on the first insulating film provided on the outside of the side surface of the multilayer.

7. The method according to claim 2, wherein

the multilayer has a side surface continued from the first surface, and

the layer containing at least one of the phosphor and the resin is provided on the side surface of the multilayer.

8. The method according to claim 2, wherein

the second insulating film surrounds a side surface of the first extraction electrode and a side surface of the second extraction electrode, and

a side surface of the layer containing at least one of the phosphor and the resin is coplanar with a side surface of the second insulating film.

9. The method according to claim 2, wherein

the part of the first metal interconnect layer extends toward the part of the second surface of the stacked part including the light emitting layer, and is provided between the first insulating film and the second insulating film.

10. The method according to claim 2, wherein

the first electrode is provided on the second surface of the multilayer.

11. The method according to claim 2, wherein

the second insulating film surrounds a side surface of the first extraction electrode and a side surface of the second extraction electrode.

12. The method according to claim 2, wherein

the first insulating film surrounds a periphery of the multilayer.

13. The method according to claim 2, wherein

the second insulating film contains a resin.

14. The method according to claim 2, wherein

the first insulating film is provided between the first electrode and the first metal interconnect layer, and between the second electrode and the second metal interconnect layer.

15. The method according to claim 2, wherein

the first electrode is provided on a part not including the light emitting layer of the multilayer, and

the first metal interconnect layer has a first surface in contact with the first electrode, and a second surface opposite to the first surface, an area of the second surface being larger than an area of the first surface.

16. The method according to claim 2, wherein

the first electrode includes stacked metal films, and

the second electrode includes stacked metal films including a reflective film, the reflective film having a reflectivity with respect to a light from the light emitting layer.

17. The method according to claim 2, wherein

the end portion of the first extraction electrode includes a solder, and the end portion of the second extraction electrode includes a solder.

18. The method according to claim 2, wherein

the first metal interconnect layer, the second metal interconnect layer, the first extraction electrode, and the second extraction electrode contain a copper.

19. The method according to claim 2, wherein

a light of the light emitting layer is emitted primarily from the first surface of the multilayer.

20. The method according to claim 2, wherein

the light emitting device includes a wafer-level package.

21. The method according to claim 2, wherein

the light emitting device includes a plurality of multilayers separated each other,

the multilayers have side surfaces continued from the first surfaces,

the first insulating film is provided on the side surfaces of the multilayers, and

the layer containing at least one of the phosphor and the resin is provided continuously on the first insulating film provided on the side surfaces of the multilayers and on the first surfaces side of the multilayers.

22. The method according to claim 21, wherein

the second insulating film is provided continuously on the second surfaces side of the multilayers.