SINGLE CRYSTAL ACOUSTIC RESONATOR AND BULK ACOUSTIC WAVE FILTER

• US 20160028367A1
• Filed: 12/10/2014
• Published: 01/28/2016
• Est. Priority Date: 07/25/2014
• Status: Active Grant

• Current Assignee: Akoustis, Inc. (Akoustis Technologies, Inc.)
• Original Assignee: Akoustis, Inc. (Akoustis Technologies, Inc.)
• Inventors: SHEALY, Jeffrey B.
• Granted Patent: US 9,912,314 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H03H 2003/023 the resonators or networks being of the membrane type
• CPC Class Codes: H03H 3/02 for the manufacture of piezoelectric or electrostrictive resonators or networks H03H3/08 takes precedence
• CPC Class Codes: H03H 9/02031 consisting of ceramic
• CPC Class Codes: H03H 9/0523 for flip-chip mounting
• CPC Class Codes: H03H 9/174 Membranes

Abstract

A method of wafer scale packaging acoustic resonator devices and an apparatus therefor. The method including providing a partially completed semiconductor substrate comprising a plurality of single crystal acoustic resonator devices provided on a silicon and carbide bearing material, each having a first electrode member, a second electrode member, and an overlying passivation material. At least one of the devices to be configured with an external connection, a repassivation material overlying the passivation material, an under metal material overlying the repassivation material. Copper pillar interconnect structures are then configured overlying the electrode members, and solder bump structures are form overlying the copper pillar interconnect structures.

Claims

1. A wafer scale package apparatus, the apparatus comprising:

a partially completed semiconductor substrate, the semiconductor substrate comprising a plurality of single crystal acoustic resonator devices, each of the devices having a first electrode member, a second electrode member, and an overlying passivation material;

for at least one of the devices to be configured with an external connection, a repassivation material overlying the passivation material, the repassivation material having a first region exposing the first electrode member and a second region exposing the second electrode member;

an under metal material overlying the repassivation material and covering the first region and the second region such that the first electrode member and the second electrode member are each in electrical and physical contact with the under metal material;

a copper pillar interconnect structure configured to fill the first region and the second region using a deposition process to form a first copper pillar structure overlying the first electrode member and a second copper pillar structure overlying the second electrode member; and

a first solder bump structure overlying the first copper pillar structure and a second solder bump structure overlying the second copper pillar structure for the single crystal acoustic resonator device to be configured with the external connection;

wherein each of the devices comprises;

a substrate member, a surface region, and a backside region, the substrate member comprising a silicon and carbide bearing material;

an epitaxial material comprising a single crystal piezo material overlying the surface region to a desired thickness;

a trench region to form an exposed portion of the surface region through a pattern provided in the epitaxial material;

a topside landing pad metal within a vicinity of the trench region and overlying the exposed portion of the surface region, the first electrode member overlying a portion of the epitaxial material, and the second electrode member overlying the topside landing pad metal;

a backside trench region exposing a backside of the epitaxial material overlying the first electrode member, and exposing a backside of the landing pad metal and a backside resonator metal material overlying the backside of the epitaxial material to form a connection from the epitaxial material to the backside of the landing pad metal to couple to the second electrode member overlying the topside landing pad metal.

2. The apparatus of claim 1 wherein the substrate member comprises single crystal silicon carbide.

3. The apparatus of claim 1 wherein the repassivation material comprises a cyclotene material having a thickness ranging from 1 um to 25 um.

4. The apparatus of claim 1 wherein the under metal material comprising a titanium containing and copper containing material.

5. The apparatus of claim 1 wherein the under metal material comprises a titanium containing and copper containing material;

wherein the under metal material has a thickness ranging from 0.1 um to 10 um.

6. The apparatus of claim 1 wherein the partially completed semiconductor substrate is configured to provide one single crystal acoustic resonator device on a first single chip from the plurality of single crystal acoustic resonator devices or is configured to provide either 2, 3, 5, 7, or 9 single crystal resonator devices provided on a second single chip;

wherein each of the solder bumps is configured on an outer peripheral region of the single chip.

7. The apparatus of claim 1 wherein the under metal material comprises a sputtering-deposited under metal material.

8. The apparatus of claim 1 wherein the copper pillar and solder material deposition process comprises a plating process.

9. The apparatus of claim 1 wherein each of the first solder bump structure and the second solder bump structure has a height of 20 um to 100 um and a width of 25 um to 150 um at a widest region.

10. The apparatus of claim 1 wherein the partially completed semiconductor substrate is configured to singulate each chip device using a saw and a break process.

11. The apparatus of claim 1 further comprising a flexible tape member.

12. The apparatus of claim 1 further comprising

a mounting substrate member;

and

a molding material overlying each of the devices.

13. The apparatus of claim 1 further comprising

a mounting substrate member;

and

a molding material overlying each of the devices;

wherein the partially completed semiconductor substrate is configured to the mounting substrate and encapsulated in the molding material.

14. A method of wafer scale packaging a grouping of single crystal acoustic resonator devices, the method comprising:

providing a partially completed semiconductor substrate, the semiconductor substrate comprising N number of single crystal acoustic resonator devices provided on a silicon and carbide bearing material, each of the N devices having a first electrode member and a second electrode member, and an overlying passivation material, the N devices being numbered R₁, R₂, . . . R_N-1, and R_N;

for at least each of devices R₁ and R_N, forming a repassivation material overlying the passivation material, the repassivation material having a first region exposing the first electrode member and a second region exposing the second electrode member;

forming an under metal material overlying the repassivation material and covering the first region and the second region such that the first electrode member and the second electrode member are each in electrical and physical contact with the under metal material;

forming a thickness of resist material overlying the under metal material to cause a substantially planarized surface region;

patterning the substantially planarized surface region of the thickness of resist material to expose a first region corresponding to the first electrode member and a second region corresponding to the second electrode member;

filling the first region and the second region using a deposition process to form a first copper pillar structure overlying the first electrode member and a second copper pillar structure overlying the second electrode member;

forming a solder material overlying the first copper pillar structure and the second copper pillar structure;

processing the thickness of resist material to substantially remove the thickness of resist material and expose the under metal material;

removing any exposed portions of the under metal material;

subjecting the solder material on the first copper pillar structure and the second copper pillar structure to cause formation of a first solder bump structure overlying the first copper pillar structure and a second solder bump structure overlying the second copper pillar structure for at least each of R₁ and R_N.

15. A method of wafer scale packaging Group III-Nitride containing devices, the method comprising:

providing a substrate member having a surface region, the substrate comprising a silicon and carbide bearing material;

forming a thickness of Group III-Nitride material overlying the surface region;

forming an insulating material overlying a portion of the thickness of Group III-Nitride material;

forming a contact region to expose a portion of the thickness of the Group III-Nitride material;

forming a pillar structure comprising a copper material within the contact region; and

forming a thickness of solder material overlying the pillar structure to cause formation of a solder bump; and

bonding the solder bump to a contact member on a substrate structure.

16. The method of claim 15 wherein the Group III-Nitride material is deposited by LPCVD;

and

further comprising using dichlorosilane (DCS), provided with or without Ammonia, to clean and prepare a surface for single crystal growth.

17. The method of claim 15 wherein the Group III-Nitride material is selected from at least one of a single crystal oxide including a high K dielectric, ZnO, or MgO.

18. The method of claim 15 wherein the Group III-Nitride material is characterized by X-ray diffraction with clear peak at a detector angle (2-θ

) associated with single crystal film and whose Full Width Half Maximum (FWHM) is measured to be less than 1.0°

.

19. A wafer scale package apparatus, the apparatus comprising:

a mounting substrate member, the mounting substrate member being optically transparent, the mounting substrate member comprising a surface region;

a single crystal acoustic resonator device configured overlying the surface region, the single crystal acoustic resonator device comprising a resonator structure and a contact structure;

a patterned solder structure overlying the surface region and configured between the single crystal acoustic resonator device and the surface region; and

a first air gap region provided from the patterned solder structure and configured between the resonator structure and a first portion of the mounting substrate member, wherein the first air gap region has a height of 10 um to 50 um;

wherein the single crystal acoustic resonator device comprises

a silicon and carbide bearing substrate member, a silicon surface region, and a silicon and carbide bearing backside region,

an epitaxial material comprising single crystal piezo material overlying the silicon and carbide bearing surface region to a desired thickness,

a trench region to form an exposed portion of the silicon and carbide bearing surface region through a pattern provided in the epitaxial material,

a topside landing pad metal within a vicinity of the trench region and overlying the exposed portion of the silicon and carbide bearing surface region, the first electrode member overlying a portion of the epitaxial material, and the second electrode member overlying the topside landing pad metal,

a backside trench region exposing a backside of the epitaxial material overlying the first electrode member, and exposing a backside of the landing pad metal and a backside resonator metal material overlying the backside of the epitaxial material to form a connection from the epitaxial material to the to the backside of the landing pad metal to couple the second electrode member overlying the topside landing pad metal;

wherein the mounting substrate member is characterized by a first coefficient of thermal expansion and wherein the silicon and carbide bearing substrate member is characterized by a second coefficient of thermal expansion, the first coefficient of thermal expansion being matched to the second coefficient of thermal expansion;

wherein the mounting substrate member comprises a borosilicate glass material or a boro-float glass material.

20. A method for packaging a resonator device, the method using a wafer scale packaging process, the method comprising:

providing a single crystal acoustic resonator device formed on a silicon and carbide bearing substrate having a first thickness, the single crystal acoustic resonator device comprising a resonator structure and a contact structure;

forming a patterned solder structure configured overlying the single crystal acoustic resonator device and the surface region to form a first air gap region provided from the patterned solder structure and configured between the resonator structure and a first portion of a mounting substrate member, wherein the first air gap region having a height of 10 um to 50 um, the patterned solder structure having a patterned upper surface region;

forming a thickness of an epoxy material overlying the patterned upper surface region, while maintaining the resonator structure free from any of the epoxy material;

positioning the mounting substrate member to the epoxy material;

curing the epoxy material to mate the single crystal acoustic resonator device to the mounting substrate member, the mounting substrate member being optically transparent, the mounting substrate member comprising a surface region; and

processing the silicon substrate to remove a portion of the silicon substrate to form a resulting silicon substrate of a second thickness, the second thickness being less than the first thickness, the resulting silicon substrate having a silicon backside region.

21. The method of claim 20 wherein the first thickness of the silicon and carbide bearing substrate ranges from 300 um to 1000 um and the second thickness ranges from 20 um to 100 um, while the silicon substrate is maintained against the mounting substrate member configured to act as a stiffener during the processing of the silicon and carbide bearing substrate, the processing comprising a grinding and polishing process;

wherein the epoxy material is a two-stage epoxy material;

wherein the height is about 25 um;

wherein the height is measured from a first perimeter region to a second perimeter region of the first air gap.

22. The method of claim 20 wherein the patterned solder structure further comprises a second air gap region provided from the patterned solder structure and configured between the contact structure and a second portion of the mounting substrate member.

23. The method of claim 20 wherein the single crystal acoustic resonator device comprises

a silicon and carbide bearing substrate member, a silicon and carbide bearing surface region, and a silicon and carbide bearing backside region,

an epitaxial material comprising single crystal piezo material overlying the silicon and carbide bearing surface region to a desired thickness,

a trench region to form an exposed portion of the silicon and carbide bearing surface region through a pattern provided in the epitaxial material,

a topside landing pad metal within a vicinity of the trench region and overlying the exposed portion of the silicon and carbide bearing surface region, the first electrode member overlying a portion of the epitaxial material, and the second electrode member overlying the topside landing pad metal,

a backside trench region exposing a backside of the epitaxial material overlying the first electrode member, and exposing a backside of the landing pad metal and a backside resonator metal material overlying the backside of the epitaxial material to form a connection from the epitaxial material to the backside of the landing pad metal to couple to the second electrode member overlying the topside landing pad metal.

24. The method of claim 20 wherein the single crystal acoustic resonator device comprises

a silicon and carbide bearing substrate member, a silicon and carbide bearing surface region, and a silicon and carbide bearing backside region,

an epitaxial material comprising single crystal piezo material overlying the silicon and carbide bearing surface region to a desired thickness,

a trench region to form an exposed portion of the silicon and carbide bearing surface region through a pattern provided in the epitaxial material,

a topside landing pad metal within a vicinity of the trench region and overlying the exposed portion of the silicon and carbide bearing surface region, the first electrode member overlying a portion of the epitaxial material, and the second electrode member overlying the topside landing pad metal,

a backside trench region exposing a backside of the epitaxial material overlying the first electrode member, and exposing a backside of the landing pad metal and a backside resonator metal material overlying the backside of the epitaxial material to form a connection from the epitaxial material to the backside of the landing pad metal to couple to the second electrode member overlying the topside landing pad metal;

and

further comprising;

forming a passivation material overlying the silicon and carbide bearing backside region;

forming a repassivation material overlying the passivation material, the repassivation material having a first region exposing the first electrode member and a second region expositing the second electrode member;

forming an under metal material overlying the repassivation material and covering the first region and the second region such that the first electrode member and the second electrode member are each in electrical and physical contact with the under metal material;

forming a thickness of resist material overlying the under metal material to cause a substantially planarized surface region;

patterning the substantially planarized surface region of the thickness of resist material to expose a first region corresponding to the first electrode member and a second region corresponding to the second electrode member;

filling the first region and the second region using a deposition process to form a first copper pillar structure overlying the first electrode member and a second copper pillar structure overlying the second electrode member;

forming a solder material overlying the first copper pillar structure and the second copper pillar structure;

processing the thickness of resist material to substantially remove the thickness of resist material and expose the under metal material;

removing any exposed portions of the under metal material; and

subjecting the solder material on the first copper pillar structure and the second copper pillar structure to cause formation of a first solder bump structure overlying the first copper pillar structure and a second solder bump structure overlying the second copper pillar structure.

25. The method of claim 24 wherein the single crystal piezo material is selected from at least one of GaN, AlN, AlGaN, InN, BN, or other group III nitrides;

wherein the epitaxial material has a thickness of greater than 0.4 um, the epitaxial material being characterized by a dislocation density of less than 10¹² defects/cm².

26. The method of claim 24 wherein the single crystal piezo material is selected from at least one of GaN, AlN, AlGaN, InN, BN, or other group III nitrides;

wherein the epitaxial material has a thickness of greater than 0.4 um, the epitaxial material being characterized by a dislocation density of less than 10¹² defects/cm².

27. The method of claim 24 wherein the single crystal piezo material is selected from at least one of a single crystal oxide including a high K dielectric, ZnO, or MgO.

28. The method of claim 24 wherein the single crystal piezo material is characterized by X-ray diffraction with clear peak at a detector angle (2-θ

) associated with single crystal film and whose Full Width Half Maximum (FWHM) is measured to be less than 1.0°

.

29. The method of claim 24 wherein the single crystal piezo material is deposited by LPCVD;

and

further comprising using dichlorosilane (DCS), provided with or without ammonia, to clean and prepare a surface for growth of the single crystal piezo material.