SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF REGULATING OUTPUT VOLTAGE THEREOF

• US 20160033981A1
• Filed: 07/22/2015
• Published: 02/04/2016
• Est. Priority Date: 07/31/2014
• Status: Active Grant

• Current Assignee: Ablic Inc. (MinebeaMitsumi Inc.)
• Original Assignee: Seiko Instruments Incorporated (Seiko Group)
• Inventors: HARADA, Hirofumi, KATO, Shinjiro
• Granted Patent: US 9,791,873 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G05F 1/468 characterised by reference voltage circuitry, e.g. soft start, remote shutdown
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

Provided is a semiconductor integrated circuit device including a memory element to which a voltage and a current is input via a regulating input terminal to be able to change a threshold voltage thereof. The semiconductor integrated circuit device can change an output voltage depending on the threshold voltage. Also provided is a method of regulating an output voltage of the semiconductor integrated circuit device, including changing an input voltage to the regulating input terminal to change the output voltage, thereby setting an arbitrary output voltage.

Claims

1. A semiconductor integrated circuit device, comprising:

a regulating input terminal;

an output voltage terminal; and

a memory element having a threshold voltage that is changed through application thereto of a voltage and a current from the regulating input terminal,

wherein an output voltage from the output voltage terminal is changeable depending on an amount of change of the threshold voltage of the memory element.

2. A semiconductor integrated circuit device, comprising:

a regulating input terminal;

an output voltage terminal;

a memory element having a threshold voltage that is changed through application thereto of a voltage and a current from the regulating input terminal; and

a reference voltage circuit comprising the memory element,

wherein a reference voltage which is output from the reference voltage circuit is changed depending on an amount of change of the threshold voltage of the memory element, and an output voltage from the output voltage terminal is changeable depending on an amount of change of the reference voltage.

3. A semiconductor integrated circuit device according to claim 2, further comprising:

an error amplifier;

a PMOS output element; and

a voltage dividing circuit comprising resistors,

wherein a source electrode of the PMOS output element is connected to a power supply terminal, a drain electrode of the PMOS output element is connected to the output voltage terminal, an output voltage that is output from the output voltage terminal is divided by the voltage dividing circuit, the divided voltage and the reference voltage that is output from the reference voltage circuit are input to the error amplifier, the input voltages are compared to each other, and the error amplifier outputs a voltage amplified depending on a difference between the input voltages to be input to a gate electrode of the PMOS output element.

4. A semiconductor integrated circuit device according to claim 2, further comprising:

a comparator; and

a voltage dividing circuit comprising resistors,

wherein a power supply voltage that is input from a power supply terminal is divided by the voltage dividing circuit, the divided voltage and the reference voltage that is output from the reference voltage circuit are input to the comparator, the input voltages are compared to each other, and a signal corresponding to a difference between the input voltages is sent from the output voltage terminal.

5. A semiconductor integrated circuit device according to claim 2, wherein the memory element comprises an N-channel MOS transistor comprising a floating gate electrode and a control gate electrode.

6. A semiconductor integrated circuit device according to claim 2, wherein the reference voltage circuit comprises the memory element as an N-channel depression type MOS transistor comprising a floating gate electrode and a control gate electrode, and an N-channel enhancement type MOS transistor.

7. A method of regulating an output voltage of a semiconductor integrated circuit device, comprising:

monitoring the output voltage while a voltage and a current are input to a memory element via a regulating input terminal; and

stopping, when the output voltage is within specification, the voltage and the current that are input via the regulating input terminal, to thereby arbitrarily set the output voltage.