PROGRAMMABLE GAIN AMPLIFIERS WITH OFFSET COMPENSATION AND TOUCH SENSOR CONTROLLER INCORPORATING THE SAME
First Claim
1. A programmable gain amplifier (PGA) circuit comprising:
- a first input resistor coupled between a first input node and a first summing node;
a second input resistor coupled between a second input node and a second summing node;
a first feedback resistor coupled between the first summing node and a first output node;
a second feedback resistor coupled between the second summing node and a second output node;
a first reference resistor coupled between a third input node and the first summing node;
a second reference resistor coupled between a fourth input node and the second summing node; and
an operational amplifier having an input coupled to the first and second summing nodes and an output coupled to the first and second output nodes, wherein at least one of the first and second reference resistors comprises an R-2R ladder circuit.
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Abstract
A programmable gain amplifier (PGA) circuit includes a first input resistor coupled between a first input node and a first summing node and a second input resistor coupled between a second input node and a second summing node. The PGA circuit further includes a first variable reference resistor coupled between a third input node and the first summing node, a second variable reference resistor coupled between a fourth input node and the second summing node, and an operational amplifier having first and second inputs coupled to respective ones of the first and second summing nodes and first and second outputs coupled to respective ones of the first and second output nodes. At least of the first and second reference resistors may include an R-2R ladder circuit.
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Citations
20 Claims
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1. A programmable gain amplifier (PGA) circuit comprising:
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a first input resistor coupled between a first input node and a first summing node; a second input resistor coupled between a second input node and a second summing node; a first feedback resistor coupled between the first summing node and a first output node; a second feedback resistor coupled between the second summing node and a second output node; a first reference resistor coupled between a third input node and the first summing node; a second reference resistor coupled between a fourth input node and the second summing node; and an operational amplifier having an input coupled to the first and second summing nodes and an output coupled to the first and second output nodes, wherein at least one of the first and second reference resistors comprises an R-2R ladder circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A programmable gain amplifier (PGA) circuit comprising:
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a first input resistor coupled between a first input node and a first summing node; a second input resistor coupled between a second input node and a second summing node; a first feedback resistor coupled between the first summing node and a first output node; a second feedback resistor coupled between the second summing node and a second output node; a first variable reference resistor coupled between a third input node and the first summing node; a second variable reference resistor coupled between a fourth input node and the second summing node; and an operational amplifier having an input coupled to the first and second summing nodes and an output coupled to the first and second output nodes. - View Dependent Claims (14, 15, 16, 18, 19)
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17. A touch sensor controller comprising:
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a demodulator configured to be coupled to a touch sensor and to generate a DC output voltage responsive to an input to the touch sensor; a programmable gain amplifier (PGA) circuit comprising; first and second input nodes coupled to an output of the demodulator; first and second output nodes; a first input resistor coupled between the first input node and a first summing node; a second input resistor coupled between the second input node and a second summing node; a first feedback resistor coupled between the first summing node and the first output node; a second feedback resistor coupled between the second summing node and the second output node; a first variable reference resistor coupled between a third input node and the first summing node; a second variable reference resistor coupled between a fourth input node and the second summing node; and an operational amplifier having an input coupled to the first and second summing nodes and an output couple to the first and second output nodes; and an analog-to-digital converter (ADC) having an input coupled to the first and second output nodes of the PGA circuit. - View Dependent Claims (20)
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Specification