MEMORY NETWORK
First Claim
Patent Images
1. A memory network comprising:
- memory nodes, wherein each memory node includes memory and control logic;
inter-node point-to-point links connecting the memory nodes with each other; and
a point-to-point link connecting a memory controller of a processor to one of the memory nodes,wherein the control logic of each memory node is to perform a memory access invoked by the memory controller of the processor and is to route data or memory access commands to a destination in the memory network.
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Abstract
According to an example, a memory network includes memory nodes. The memory nodes may each include memory and control logic. The control logic may operate the memory node as a destination for a memory access invoked by a processor connected to the memory network and may operate the memory node as a router to route data or memory access commands to a destination in the memory network.
52 Citations
15 Claims
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1. A memory network comprising:
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memory nodes, wherein each memory node includes memory and control logic; inter-node point-to-point links connecting the memory nodes with each other; and a point-to-point link connecting a memory controller of a processor to one of the memory nodes, wherein the control logic of each memory node is to perform a memory access invoked by the memory controller of the processor and is to route data or memory access commands to a destination in the memory network. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A memory node in a memory network, the memory node comprising;
- control logic; and
memory, wherein the control logic is to operate the memory node as a destination for a memory access invoked by a memory controller of a processor and to operate the memory node as a router to route memory access commands to a destination in the memory network. - View Dependent Claims (12, 13, 14)
- control logic; and
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15. An integrated circuit comprising:
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a processor; and a memory controller for the processor connected to a memory network via a point-to-point link, wherein the memory network includes memory nodes, each memory node including memory and control logic, and inter-node point-to-point links connecting the memory nodes with each other, and the control logic of each memory node is to operate the memory node as a destination for a memory access invoked by the memory controller of the processor and to operate the memory node as a router to route data or memory access commands to a destination, and wherein the processor is to prioritize memory accesses in the memory network or is to move data for memory accesses to near memory in the memory network to minimize latency for memory accesses.
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Specification