MEMORY CONTROLLER CONFIGURED TO CONTROL DATA SANITIZATION AND MEMORY SYSTEM INCLUDING THE SAME

• US 20160034217A1
• Filed: 04/30/2015
• Published: 02/04/2016
• Est. Priority Date: 07/31/2014
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KWON, MOON-SANG, KIM, JI-SOO, HAN, MYEONG-JIN
• Application Number:
  US14/700,606
• Publication Number:
  US 20160034217A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/0622 in relation to access
• CPC Class Codes: G06F 3/0638 Organizing or formatting or addressing of data
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

Provided is a memory controller configured to control data sanitization. The memory controller includes a sanitization information storing unit configured to store first information or second information in a non-volatile manner, and a control unit configured to store the first information in the sanitization information storing unit when sanitization of data stored in a non-volatile memory has completed in response to a sanitization command of a host and store the second information in the sanitization information storing unit in response to a write command of the host.

Claims

1. A memory controller comprising:

a sanitization information storing unit configured to store first information or second information in a non-volatile manner; and

a control unit configured to store the first information in the sanitization information storing unit when sanitization of data stored in a non-volatile memory has completed in response to a sanitization command of a host and store the second information in the sanitization information storing unit in response to a write command of the host.

2. The memory controller of claim 1, wherein the control unit reads information stored in the sanitization information storing unit in response to a check command of the host and transmits the read information to the host.

3. The memory controller of claim 1, wherein the control unit reads information stored in the sanitization information storing unit and outputs a control signal based on the read information.

4. The memory controller of claim 1, wherein the control unit is a processor configured to execute a plurality of instructions and access the sanitization information storing unit, and

the memory controller further comprises read-only memory (ROM) that stores the plurality of instructions and is accessed by the processor.

5. The memory controller of claim 1, wherein the first information includes information regarding types of the sanitization of the data.

6. The memory controller of claim 5, wherein the types of the sanitization of the data comprises a Secure Erase or a Crypto Erase.

7. The memory controller of claim 1, wherein the second information includes information regarding the size of data stored in the non-volatile memory in response to at least one write command of the host.

8. A memory system comprising:

a non-volatile memory; and

a memory controller configured to control the non-volatile memory,

wherein the memory controller comprises;

a sanitization information storing unit configured to store first information or second information in a non-volatile manner; and

a control unit configured to store the first information in the sanitization information storing unit when sanitization of data stored in the non-volatile memory has completed in response to a sanitization command of a host and store the second information in the sanitization information storing unit in response to a write command of the host.

9. The memory system of claim 8, wherein the control unit reads information stored in the sanitization information storing unit in response to a check command of the host and transmits the read information to the host.

10. The memory system of claim 8, wherein the control unit reads information stored in the sanitization information storing unit and outputs a control signal based on the read information, and

the memory system further comprises an indicator configured to output a visible signal based on the control signal.

11. The memory system of claim 10, wherein the indicator comprises a light-emitting diode (LED) or an electronic ink (e-ink) panel.

12. The memory system of claim 8, further comprising a wireless communication module connected to the sanitization information storing unit,

wherein the wireless communication module outputs a wireless signal based on information stored in the sanitization information storing unit.

13. The memory system of claim 8, further comprising a sensing unit connected to the sanitization information storing unit and configured to sense an invasive attack against the memory system,

wherein the sanitization information storing unit is re-configured to output a signal corresponding to the second information or third information that is different from the first information and the second information when the sensing unit senses the invasive attack.

14. The memory system of claim 8, wherein the non-volatile memory comprises a plurality of flash memory devices each of which includes a three-dimensional memory array.

15. The memory system of claim 14, wherein the three-dimensional memory array comprises a portion that is monolithically formed in one or more physical levels of memory cells having active areas disposed above a silicon substrate.

16. A memory system comprising:

a non-volatile memory;

a memory controller; and

a sensing unit configured to output a message to the memory controller when the sensing unit senses a physical attack against the memory system,

wherein the memory controller is configured to sanitize data stored within the non-volatile memory and store information within the memory controller indicating the data has been sanitized, in response to a command received from a host, and

wherein the memory controller is configured to update the information to indicate the data has not been sanitized in response to receipt of the message.

17. The memory system of claim 16, wherein the sensing unit is configured to sense whether an attempt to dismantle a case of the memory system has occurred.

18. The memory system of claim 16, wherein the memory controller is configured to update the information to indicate the data has not been sanitized after receiving a command from the host to write data into the non-volatile memory.

19. The memory system of claim 16, further comprising an electronic ink panel or a light emitting diode to visibly indicate whether the data has been sanitized.

20. The memory system of claim 16, wherein the memory controller sanitizes the data by performing one of a Clear or a Purge action on the non-volatile memory.