MEMORY SYSTEM AND CONTROL METHOD THEREOF

• US 20160034221A1
• Filed: 03/06/2015
• Published: 02/04/2016
• Est. Priority Date: 07/31/2014
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ueki, Katsuhiko, Yoshii, Kenichiro, Zettsu, Tatsuya, Kojima, Yoshihisa, Yao, Hiroshi, Magaki, Ikuo
• Granted Patent: US 10,747,449 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

According to one embodiment, a memory system is provided with a nonvolatile memory, a controller, a volatile memory and an address translation table. The address translation table includes a high level and a plurality of low levels. The high level indicates positions in the nonvolatile memory in which the low levels are recorded. The low levels indicate positions in the nonvolatile memory in which data is recorded. The controller holds the high level of the address translation table in the first area of the volatile memory, and shuts off the supply of power to the second area of the volatile memory based on a transition from a normal-power state to a low-power state.

Claims

1. A memory system comprising:

a nonvolatile memory having a plurality of physical blocks, and each of the physical blocks being an erasure unit;

a controller configured to translate a logical address supplied from a host into a physical address to access the nonvolatile memory;

a volatile memory including a first area and a second area; and

an address translation table configured to translate the logical address into the physical address, the address translation table including first data and second data, the first data indicating positions in the nonvolatile memory in which the second data is stored, the second data indicating positions in the nonvolatile memory in which data is stored,

wherein the controller is configured to store the first data of the address translation table in the first area of the volatile memory, to refresh the first area and the second area of the volatile memory during a first power mode, and to refresh only the first area of the volatile memory during a second power mode.

2. The system according to claim 1, wherein the volatile memory comprises a single volatile memory device, and the first area and the second area correspond to memory cell arrays contained in the single volatile memory device.

3. The system according to claim 1, wherein the controller shuts off supply of power to the second area of the volatile memory based on a transition from the first power mode to the second power mode.

4. The system according to claim 1, wherein the first power mode is a normal-power state, and the second power mode is a low-power state.

5. The system according to claim 1, wherein the controller stores the second data of the address translation table in the volatile memory, the first data of the address translation table indicating positions in the volatile memory in which the second data of the address translation table are stored.

6. The system according to claim 1, further comprising:

a first table showing correspondence between a logical block and a plurality of groups of physical blocks in the nonvolatile memory, the logical block indicating the groups of physical blocks; and

a valid data amount table holding data indicative of a valid data amount in the logical block,

wherein the controller is configured to store, in the first area of the volatile memory, at least one of the first table and the valid data amount table.

7. The system according to claim 1, further comprising a second table showing defective portions in the nonvolatile memory,

wherein

the second table includes first data and second data, the first data of the second table indicating positions in the nonvolatile memory and volatile memory in which the second data of the second table are stored;

and

the controller is configured to store the first data of the second table in the first area of the volatile memory.

8. The system according to claim 1, wherein the controller is configured to transition to the second power mode when there is no data access request from the host for a predetermined period of time.

9. The system according to claim 1, wherein the controller is configured to transition to the second power mode in response to a host request.

10. The system according to claim 4, wherein

the second data of the address translation table that have most recently been used are assigned a higher priority;

and

the controller is configured to store the second data of the address translation table with higher priority in the first area of the volatile memory.

11. The system according to claim 7, wherein

the second data of the second table that have most recently been used are assigned a higher priority;

and

the controller is configured to store the second data of the second table with higher priority in the first area of the volatile memory.

12. The system according to claim 11, wherein

the controller is configured to store the second data of the second table with higher priority in the first area of the volatile memory during the second power mode.

13. The system according to claim 10, wherein

the controller is configured to store the second data of the address translation table with higher priority in the first area of the volatile memory during the second power mode.

14. The system according to claim 1, further comprising a second table, the second table including first data and second data, the first data of the second table being stored in the first area of the volatile memory and indicating positions in the nonvolatile memory and the volatile memory in which the second data of the second table is stored, the second data of the second table indicating defective portions in the nonvolatile memory,

the nonvolatile memory comprises:

a first area;

a second area; and

a third area,

wherein

the first area of the nonvolatile memory storing at least user data;

the defective portions in the first area of the nonvolatile memory are indicated by the second data of the second table, and the second area of the nonvolatile memory stores the second data of the second table; and

the defective portions in the second area of the nonvolatile memory are indicated by the first data of the second table, and the third area of the nonvolatile memory stores the first data of the second table.

15. The system according to claim 7, wherein the controller is configured to store data with higher priority in the first area of the volatile memory,

wherein data indicating the defective portions of the nonvolatile memory used to store the second data of the address translation table has higher priority compared to the data indicating the defective portions of the nonvolatile memory used to store user data.

16. The system according to claim 7, wherein when the host requests a transition to the second power mode, or when the host does not issue a request to read user data for a predetermined period of time, the controller is configured to store in the first area of the volatile memory,

data indicative of a defective portion of a physical block to which user data requested by the host is to be written,

data indicative of a defective portion of a physical block to which user data is moved by garbage collection and is to be written, and

data indicative of a defective portion of a physical block to which the address translation table is to be written.

17. The system according to claim 1, wherein the controller is configured to store in the first area of the volatile memory data, indicative of a state of garbage collection during the second power mode.

18. The system according to claim 1, wherein when supply of power from an external power supply is shut off, the controller is configured to shut off supply of power to the second area of the volatile memory that stores data already stored in the nonvolatile memory.

19. A memory system comprising:

a nonvolatile memory having a plurality of physical blocks, and each of the physical blocks being an erasure unit;

a front end configured to receive a read request and a write request of data designated by a logical address, from a host;

a back end configured to translate the logical address to a physical address to access the nonvolatile memory, based on a request from the front end;

a volatile memory including a first area and a second area; and

an address translation table configured to translate the logical address into the physical address, the address translation table including first data and second data, the first data indicating positions in the nonvolatile memory in which the second data is stored, the second data indicating positions in the nonvolatile memory in which data is stored,

wherein the back end is configured to store the first data of the address translation table in the first area of the volatile memory, to refresh the first area and the second area of the volatile memory during a first power mode, and to refresh only the first area of the volatile memory during a second power mode.

20. The system according to claim 19, wherein the volatile memory comprises a single memory device, and the first area and the second area correspond to memory cell arrays contained in the single volatile memory device.

21. The system according to claim 19, wherein the back end is configured to shut off supply of power to the second area of the volatile memory based on a transition from the first power mode to the second power mode.

22. The system according to claim 19, wherein the first power mode is a normal-power state, and the second power mode is a low-power state.

23. The system according to claim 19, wherein the back end is configured to store the second data of the address translation table in the volatile memory, the first data of the address translation table indicating positions in the volatile memory in which the second data of the address translation table are stored.

24. The system according to claim 19, further comprising:

a first table showing correspondence between a logical block and a plurality of groups of physical blocks in the nonvolatile memory, the logical block indicating a structure of the groups of physical blocks; and

a valid data amount table holding data indicative of a valid data amount in the logical block,

wherein the back end is configured to store, in the first area of the volatile memory, at least one of the first table and the valid data amount table.

25. The system according to claim 19, further comprising a second table showing defective portions in the nonvolatile memory,

wherein

the second table includes first data and second data, the first data of the second table indicating positions in the nonvolatile memory and volatile memory in which the second data of the second table are stored;

and

the back end is configured to store the first data of the second table in the first area of the volatile memory.

26. The system according to claim 19, wherein the back end is configured to transition to the second power mode when there is no data access request from the host for a predetermined period of time.

27. The system according to claim 19, wherein the back end is configured to transition to the second power mode in response to a host request.

28. The system according to claim 22, wherein

the second data of the address translation table that have most recently been used are assigned to a higher priority;

and

the back end is configured to store the second data of the address translation table with higher priority in the first area of the volatile memory.

29. The system according to claim 25, wherein

the second data of the second table that have most recently been used are assigned to a higher priority;

and

the back end is configured to store the second data of the second table with higher priority in the first area of the volatile memory.

30. The system according to claim 29, wherein

the back end is configured to store the second data of the second table with higher priority in the first area of the volatile memory during the second power mode.

31. The system according to claim 28, wherein

the back end is configured to store the second data of the address translation table with higher priority during the second power mode.

32. The system according to claim 19, further comprising a second table, the second table including first data and second data, the first data of the second table being stored in the first area of the volatile memory and indicating positions in the nonvolatile memory and the volatile memory in which the second data of the second table is stored, the second data of the second table indicating defective portions in the nonvolatile memory,

the nonvolatile memory comprises:

a first area;

a second area; and

a third area,

wherein

the first area of the nonvolatile memory storing at least user data;

the defective portions in the first area of the nonvolatile memory are indicated by the second data of the second table, and the second area of the nonvolatile memory stores the second data of the second table; and

the defective portions in the second area of the nonvolatile memory are indicated by the first data of the second table, and the third area of the nonvolatile memory stores the first data of the second table.

33. The system according to claim 25, wherein the back end is configured to store data with higher priority in the first area of the volatile memory,

wherein data indicating the defective portions of the nonvolatile memory used to store the second data of the address translation table has higher priority compared to data indicating the defective portions of the nonvolatile memory used to store user data.

34. The system according to claim 25, wherein when the host requests a transition to the second power mode, or when the host does not issue a request to read user data for a predetermined period of time, the back end is configured to store in the first area of the volatile memory,

data indicative of a defective portion of a physical block to which user data requested by the host is to be written,

data indicative of a defective portion of a physical block to which user data is moved by garbage collection and to be written, and

data indicative of a defective portion of a physical block to which the address translation table is to be written.

35. The system according to claim 19, wherein the back end is configured to store, in the first area of the volatile memory, data indicative of a state of garbage collection during the second power mode.

36. The system according to claim 19, wherein when supply of power from an external power supply is shut off, the back end is configured to shut off supply of power to the second area of the volatile memory that stores data already stored in the nonvolatile memory.

37. A control method of a memory system comprising:

storing first data of an address translation table in a first area of a volatile memory, the first data indicating positions in a nonvolatile memory in which second data of the address translation table are stored, the second data indicating positions in the nonvolatile memory in which data is stored;

refreshing the first area and a second area of the volatile memory during a first power mode; and

refreshing only the first area of the volatile memory during a second power mode.

38. The method according to claim 37, wherein the volatile memory comprises a single volatile memory device, and the first area and the second area correspond to memory cell arrays contained in the single volatile memory device.

39. The method according to claim 37, further comprising:

shutting off supply of power to the second area of the volatile memory based on a transition from the first power mode to the second power mode.

40. The method according to claim 37, wherein the first power mode is a normal-power state, and the second power mode is a low-power state.

41. The method according to claim 37, further comprising:

storing the second data of the address translation table in the first area of the volatile memory,

wherein the first data of the address translation table indicates positions in the volatile memory in which the second data of the address translation table are stored.

42. The method according to claim 37, further comprising:

storing, during the second power mode, at least one of a first table, a valid data amount table, and a second table, in the first area of the volatile memory,

the first table showing correspondence between a logical block and a plurality of groups of physical blocks in the nonvolatile memory, the logical block indicating a structure of the groups of physical blocks in the nonvolatile memory;

the valid data amount table holding data indicative of a valid data amount in the logical block; and

the second table indicating defective portions of the nonvolatile memory,

wherein the second table includes first data and second data, the first data of the second table indicating positions in the nonvolatile memory and volatile memory in which the second data of the second table are stored.