DISPLAY PANEL AND DISPLAY DEVICE HAVING THE SAME

• US 20160035307A1
• Filed: 06/02/2015
• Published: 02/04/2016
• Est. Priority Date: 07/30/2014
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Jeon, Sang Jin, Jung, Kwang Chul, Cho, Se Hyoung
• Granted Patent: US 9,691,791 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0281 Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
• CPC Class Codes: G09G 2320/0209 Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

A display device includes: a substrate partitioned into a display area including a plurality of pixels for displaying images thereon and a non-display area around the display area; a plurality of first gate lines and a plurality of data lines extended in one direction on the display area; a plurality of pads on one side of the non-display area; a plurality of gate fan-out lines, each coupling one of the first gate lines and a corresponding one of the pads; and a plurality of data fan-out lines, each coupling one of the data lines and a corresponding one of the pads, wherein the gate fan-out lines and the data fan-out lines may be alternately disposed.

Claims

1. A display panel comprising:

a substrate partitioned into a display area comprising a plurality of pixels for displaying images thereon and a non-display area around the display area;

a plurality of first gate lines and a plurality of data lines extended in one direction on the display area;

a plurality of pads on one side of the non-display area;

a plurality of gate fan-out lines, each coupling one of the first gate lines and a corresponding one of the pads; and

a plurality of data fan-out lines, each coupling one of the data lines and a corresponding one of the pads,

wherein the gate fan-out lines and the data fan-out lines are alternately disposed.

2. The display panel of claim 1, wherein the pads are on only one side of the non-display area.

3. The display panel of claim 1, wherein the gate fan-out lines do not overlap the data fan-out lines.

4. The display panel of claim 3, wherein the gate fan-out lines and the data fan-out lines are on a same layer.

5. The display panel of claim 1, wherein each of the plurality of gate fan-out lines has substantially a same resistance value.

6. The display panel of claim 5, wherein each of the plurality of gate fan-out lines has substantially a same length.

7. The display panel of claim 1, wherein each of the plurality of data fan-out lines has substantially a same resistance value.

8. The display panel of claim 7, wherein each of the plurality of data fan-out lines has substantially a same length.

9. The display panel of claim 1, wherein at least one of the gate fan-out lines corresponds to a plurality of data fan-out lines.

10. The display panel of claim 1, further comprising a plurality of second gate lines insulated from the first gate lines and the data lines by an insulating layer and crossing the first gate lines,

wherein one of the first gate lines and a corresponding one of the second gate lines are coupled through a contact hole in an overlap area.

11. A display device comprising:

a substrate partitioned into a display area comprising a plurality of pixels for displaying images thereon and a non-display area around the display area;

a plurality of first gate lines and a plurality of data lines extended in one direction on the display area;

a plurality of pads on one side of the non-display area;

a plurality of gate fan-out lines, each coupling one of the first gate lines and a corresponding one of the pads;

a plurality of data fan-out lines, each coupling one of the data lines and a corresponding one of the pads; and

at least one driver integrated circuit coupled to the plurality of pads and configured to apply scan signals and data signals,

wherein the gate fan-out lines and the data fan-out lines are alternately disposed.

12. The display device of claim 11, wherein the driver integrated circuit comprises:

a gate driver logic configured to generate scan signals, and

a data driver logic configured to generate data voltages.

13. The display device of claim 11, wherein the driver integrated circuit comprises:

a gate driver integrated circuit, and

a data driver integrated circuit.

14. The display device of claim 11,

wherein the at least one driver integrated circuit comprises a plurality of driver integrated circuits, and

wherein the driver integrated circuits are at substantially equal distances from each other.

15. The display device of claim 11, wherein the gate fan-out lines do not overlap the data fan-out lines.

16. The display device of claim 15, wherein the gate fan-out lines and the data fan-out lines are on a same layer.

17. The display device of claim 11,

wherein each of the plurality of gate fan-out lines has substantially a same resistance value, and

wherein each of the plurality of data fan-out lines has substantially a same resistance value.

18. The display device of claim 17,

wherein each of the plurality of gate fan-out lines has substantially a same length, and

wherein each of the plurality of data fan-out lines has substantially a same length.

19. The display device of claim 11, wherein at least one of the gate fan-out lines corresponds to a plurality of data fan-out lines.

20. The display device of claim 11, further comprising:

a plurality of second gate lines insulated from the first gate lines and the data lines by an insulating layer and crossing the first gate lines,

wherein one of the first gate lines and a corresponding one of the second gate lines are coupled through a contact hole in an overlap area.