MEMORY DEVICE ARCHITECTURE

• US 20160035418A1
• Filed: 10/16/2015
• Published: 02/04/2016
• Est. Priority Date: 10/12/2012
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Castro, Hernan A., Flores, Everardo Torres, Hirst, Jeremy M.
• Granted Patent: US 9,734,900 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H10B 63/24 of the Ovonic threshold switching type
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.

Claims

1. A method, comprising:

forming a plurality of row drivers and a plurality of column drivers below and within a footprint of an array of memory cells.

2. The method of claim 1, wherein forming the row drivers and column drivers comprises partitioning the row drivers into a plurality of subsets of row drivers and partitioning the column drivers into a plurality of subsets of column drivers and interspersing the subsets of row drivers among the subsets of column drivers.

3. The method of claim 2, wherein forming the row drivers and column drivers comprises forming word line drivers and bit line drivers.

4. The method of claim 2, wherein forming the row drivers and column drivers comprises distributing the row drivers and column drivers across the footprint of the memory array in disjointed row driver regions and disjointed column driver regions, such that row electrodes connecting the row drivers to memory cells of the memory array are staggered, and column electrodes connecting the column drivers to the memory cells of the memory array are staggered.

5. The method of claim 4, wherein distributing the row drivers and column drivers comprises grouping row drivers into the row driver regions and grouping column drivers into the column driver regions such that the row electrodes and the column electrodes are staggered in bundles.

6. The method of claim 4, further comprising connecting each row electrode to a central part of one of the row driver regions and connecting each column electrode to a central part of one of the column driver regions.

7. The method of claim 4, wherein distributing row drivers and column drivers comprises forming a repeating quilt-like pattern of the row driver regions and column driver regions.

8. The method of claim 7, wherein forming the repeating pattern comprises forming row driver regions such that they border on column driver regions.

9. The method of claim 1, further comprising:

forming one or more interconnect levels over a circuit level, the circuit level comprising the row drivers and the column drivers; and

forming the array of memory cells over the one or more interconnect levels.

10. The method of claim 9, wherein the forming the array of memory cells over the one or more interconnect levels comprises forming an array of phase change memory cells between row electrodes and column electrodes in a cross-point memory array.

11. The method of claim 9, wherein forming the array of memory cells over the one or more interconnect levels comprises scaling the array to cover logic circuitry in the circuit level for the array.

12. A method of forming a memory device, comprising:

forming a plurality electrode line drivers distributed within a footprint of an array of memory cells; and

forming a plurality of electrode lines each electrically connected to and laterally traversing at least one of the electrode line drivers at a different vertical level from the plurality of electrode line drivers.

13. The method of claim 12, wherein each electrode line vertically connects to one of the electrode line drivers at a central location of the each electrode line.

14. The method of claim 12, wherein each electrode line driver is elongated in a first direction and the plurality of electrode lines extend in a second direction crossing the first direction.

15. The method of claim 14, further comprising forming a plurality of second electrode line drivers distributed within the footprint, and forming a plurality of second electrode lines crossing the first electrode lines, wherein each second electrode line is electrically connected to and laterally traverses at least one of the second electrode line drivers at a vertical level different from the second plurality of electrode line drivers.

16. The method of claim 15, wherein each of the second electrode line drivers is elongated in the second direction and the plurality of second electrode lines extend in the first direction.

17. The method of claim 12, wherein the footprint is subdivided into a plurality of sub array regions that have a repeating pattern of distributed electrode line drivers.

18. A method, comprising:

forming a memory array; and

forming a plurality of first electrode drivers distributed across a footprint of the memory array in a plurality of disjointed first electrode driver regions.

19. The method of claim 18, wherein forming the first electrode drivers in the disjointed first electrode driver regions include arranging the first electrode driver regions in a repeating pattern of sub array regions across the footprint.

20. The method of claim 19, further comprising forming a plurality of second electrode drivers distributed across the footprint in a plurality of disjointed second electrode driver regions by arranging the disjointed second electrode driver regions in the repeating pattern of sub array regions.

21. The method of claim 20, wherein arranging the disjointed first electrode driver regions and the disjointed second electrode driver regions in the repeating pattern includes alternating the disjointed first electrode driver regions with the disjointed second electrode driver regions in at least one of a first electrode lengthwise direction and a second electrode lengthwise direction.

22. The method of claim 20, wherein arranging the disjointed first electrode driver regions and the disjointed second electrode driver regions includes forming at least a portion of one of the disjointed first electrode driver regions and at least a portion of one of the disjointed second electrode driver regions within a sub array region.

23. The method of claim 20, wherein forming the memory array comprises forming staggered first electrodes connecting the first electrode drivers to memory cells of the memory array, and forming staggered second electrodes connecting the second electrode drivers to the memory cells.

24. The method of claim 18, wherein forming the memory array includes forming an array of phase change memory cells.

25. The method of claim 24, wherein forming the memory array includes forming a multi-deck array of phase change memory cells.