×

MEMORY ARRAY WITH RAM AND EMBEDDED ROM

  • US 20160035433A1
  • Filed: 07/30/2014
  • Published: 02/04/2016
  • Est. Priority Date: 07/30/2014
  • Status: Active Grant
First Claim
Patent Images

1. A memory array, comprising:

  • a plurality of RAM cells, each having a RAM cell structure with a first power terminal and a second power terminal and configured to operate as a RAM cell when the memory array is in a RAM mode;

    a ROM cell comprising said RAM cell structure having at least one transistor that is modified so that said ROM cell settles to a predetermined logic state; and

    a ROM enable circuit that enables first and second bit lines of said ROM cell to adjust supply voltage provided to said first and second power terminals of each of said plurality of RAM cells so that said plurality of RAM cells each settle to a predetermined logic state when the memory array is in a ROM mode.

View all claims
  • 15 Assignments
Timeline View
Assignment View
    ×
    ×