Strained Channel of Gate-All-Around Transistor

• US 20160035849A1
• Filed: 07/30/2014
• Published: 02/04/2016
• Est. Priority Date: 07/30/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Liu, Chi-Wen, Wang, Chao-Hsiung
• Granted Patent: US 9,741,810 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

The disclosure relates to a semiconductor device. An exemplary structure for a nanowire structure comprises a first semiconductor material having a first lattice constant and a first linear thermal expansion constant; and a second semiconductor material having a second lattice constant and a second linear thermal expansion constant surrounding the first semiconductor material, wherein a ratio of the first lattice constant to the second lattice constant is from 0.98 to 1.02, wherein a ratio of the first linear thermal expansion constant to the second linear thermal expansion constant is greater than 1.2 or less than 0.8.

Claims

1. A nanowire structure comprising:

a first semiconductor material having a first lattice constant and a first linear thermal expansion constant; and

a second semiconductor material having a second lattice constant and a second linear thermal expansion constant surrounding the first semiconductor material,

wherein a ratio of the first lattice constant to the second lattice constant is from 0.98 to 1.02, and wherein a ratio of the first linear thermal expansion constant to the second linear thermal expansion constant is greater than 1.2 or less than 0.8.

2. The nanowire structure of claim 1, wherein the cross-sectional shape of the first semiconductor material comprises square or rectangular.

3. The nanowire structure of claim 1, wherein the cross-sectional shape of the first semiconductor material comprises circle or ellipse.

4. The nanowire structure of claim 1, wherein one of the first semiconductor material and the second semiconductor material is Si and the other comprises AlP or GaP.

5. The nanowire structure of claim 1, wherein one of the first semiconductor material and the second semiconductor material is AlAs and the other comprises Ge or GaAs.

6. The nanowire structure of claim 1, wherein one of the first semiconductor material and the second semiconductor material is GaSb and the other comprises InAs or AlSb.

7. The nanowire structure of claim 1, wherein a ratio of a thickness of the second semiconductor material to a thickness of the nanowire structure is from 0.05 to 0.5.

8. A semiconductor device comprising:

a source region and a drain region;

a nanowire structure between the source region and drain region comprising

a first semiconductor material having a first lattice constant and a first linear thermal expansion constant, and

a second semiconductor material having a second lattice constant and a second linear thermal expansion constant surrounding the first semiconductor material, wherein a ratio of the first lattice constant to the second lattice constant is from 0.98 to 1.02, wherein a ratio of the first linear thermal expansion constant to the second linear thermal expansion constant is greater than 1.2 or less than 0.8; and

a metal gate surrounding a channel portion of the nanowire structure.

9. The semiconductor device of claim 8, wherein the cross-sectional shape of the first semiconductor material comprises square or rectangular.

10. The semiconductor device of claim 8, wherein the cross-sectional shape of the first semiconductor material comprises circle or ellipse.

11. The semiconductor device of claim 8, wherein one of the first semiconductor material and the second semiconductor material is Si and the other comprises AlP or GaP.

12. The semiconductor device of claim 8, wherein one of the first semiconductor material and the second semiconductor material is AlAs and the other comprises Ge or GaAs.

13. The semiconductor device of claim 8, wherein one of the first semiconductor material and the second semiconductor material is GaSb and the other comprises InAs or AlSb.

14. The semiconductor device of claim 8, wherein a ratio of a thickness of the second semiconductor material to a thickness of the nanowire structure is from 0.05 to 0.5.

15. The semiconductor device of claim 8, wherein a lattice constant of the source region is greater than the lattice constant of the first semiconductor material.

16. The semiconductor device of claim 8, wherein a lattice constant of the source region is less than the lattice constant of the first semiconductor material.

17. The semiconductor device of claim 8, wherein the source region comprise SiGe.

18. The semiconductor device of claim 8, wherein the source region comprise SiC.

19-20. -20. (canceled)

21. A Gate-All-Around (GAA) transistor comprising:

an epitaxial source region;

an epitaxial drain region;

a nanowire structure disposed between and connected to the source and the drain regions, the nanowire structure comprising;

a first semiconductor material with a first lattice constant and a first linear thermal expansion constant; and

a second semiconductor material around the first semiconductor material, the second semiconductor material having a second lattice constant substantially matched to the first lattice constant, and a second linear thermal expansion constant different from the first linear thermal expansion constant,

wherein a third lattice constant of the source region is different from the first lattice constant of the first semiconductor material; and

a metal gate around a middle portion of the nanowire structure.

22. the GAA transistor of claim 21, wherein a ratio of the first lattice constant to the second lattice constant is from 0.98 to 1.02, and wherein a ratio of the first linear thermal expansion constant to the second linear thermal expansion constant is greater than 1.2 or less than 0.8.