METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

• US 20160035861A1
• Filed: 04/27/2015
• Published: 02/04/2016
• Est. Priority Date: 08/04/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Dong-Suk Shin, Jae-Gon Lee, Pan-Kwi Park, Seok-Jun Won, Weon-Hong Kim
• Inventors: WON, SEOK-JUN, PARK, PAN-KWI, SHIN, DONG-SUK, KIM, WEON-HONG, LEE, JAE-GON
• Granted Patent: US 9,583,592 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02057 Cleaning during device manufacture
• CPC Class Codes: H01L 21/0206 during, before or after processing of insulating layers
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02247 formation by nitridation, e.g. nitridation of the substrate
• CPC Class Codes: H01L 21/02332 into an oxide layer, e.g. changing SiO to SiON
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

In a method of manufacturing a semiconductor device, a dummy gate structure is formed on a substrate. A first spacer layer is formed on the substrate to cover the dummy gate structure. A nitridation process is performed on the first spacer layer. An upper portion of the substrate adjacent to the dummy gate structure is removed to form a trench. An inner wall of the trench is cleaned. An epitaxial layer is formed to fill the trench. The dummy gate structure is replaced with a gate structure.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

forming a dummy gate structure on a substrate;

forming a spacer layer on the substrate including over the dummy gate structure;

nitriding the spacer layer;

forming a trench in the substrate by removing an upper portion of the substrate adjacent to the dummy gate structure;

cleaning an interior surface that defines the trench;

forming an epitaxial layer in the trench; and

replacing the dummy gate structure with a gate structure.

2. The method of claim 1, prior to nitriding the spacer layer, further comprising:

forming a photoresist pattern on the substrate to expose an upper portion of the substrate;

forming an impurity region at the upper portion of the substrate using the photoresist pattern as a mask; and

removing the photoresist pattern by an ashing process and/or a stripping process.

3. The method of claim 2, wherein the spacer layer is formed of silicon nitride, and wherein removing the photoresist pattern includes oxidizing the first spacer layer.

4. The method of claim 1, wherein the nitriding is performed using nitrogen (N₂) and/or ammonia (NH₃).

5. The method of claim 1, further comprising cleaning the spacer layer before the spacer layer is nitrided.

6. The method of claim 5, wherein the cleaning of the spacer layer decreases the thickness of the spacer layer.

7. The method of claim 5, wherein the cleaning is a dry cleaning process using gaseous ammonia (NH₃) and/or nitrogen trifluoride (NF₃) plasma, or a wet cleaning process using hydrogen fluoride (HF) and/or buffered oxide etch (BOE).

8. The method of claim 1, further cleaning the spacer layer after the first spacer layer is nitrided.

9. The method of claim 1, wherein the cleaning of the interior surface defining the trench is a wet etch process using ammonia hydroxide (NH₄OH) as an etching solution.

10. The method of claim 1, therein the spacer layer is a first spacer layer, further comprising:

forming a second spacer layer on the first spacer layer after the first spacer layer is nitrided; and

anisotropically etching the first and second spacer layers to form first and second spacers, respectively, sequentially stacked on a side surface of the dummy gate structure.

11. The method of claim 10, wherein the second spacer layer is formed of silicon nitride and to a thickness greater than that of the first spacer layer.

12. The method of claim 1, wherein forming the dummy gate structure includes:

forming a dummy gate insulation layer of silicon oxide on the substrate;

forming a dummy gate electrode layer comprising polysilicon on the dummy gate insulation layer;

forming a hard mask to of silicon nitride on the dummy gate electrode layer; and

sequentially etching the dummy gate electrode layer and the dummy gate insulation layer using the hard mask as an etching mask to form a dummy gate insulation layer pattern, a dummy gate electrode, and a hard mask sequentially stacked on the substrate.

13. The method of claim 12, further comprising anisotropically etching the spacer layer to form a spacer on a side surface of the dummy gate structure after the spacer layer is nitrided, and

wherein replacing the dummy gate structure with the gate structure includes:

removing the hard mask, the dummy gate electrode and the dummy gate insulation layer pattern to form an opening exposing an inner wall surface of the spacer and a top surface of the substrate; and

forming a gate insulation layer pattern, a high-k dielectric layer pattern and a gate electrode that fills the opening and are sequentially stacked on the exposed top surface of the substrate.

14. The method of claim 13, further comprising removing part of the exposed first spacer to enlarge the opening.

15. The method of claim 14, wherein the part of the first spacer to enlarge the opening comprises performing a dry process using gaseous ammonia (NH₃) and/or nitrogen trifluoride (NF₃) plasma, or a wet process using hydrogen fluoride (HF) and/or buffered oxide etch (BOE).

16. A method of manufacturing a semiconductor device, the method comprising:

forming first and second dummy gate structures on first and second regions, respectively, of a substrate;

forming a spacer layer on the substrate to cover the first and second dummy gate structures;

nitriding the spacer layer;

forming a first trench in the substrate by removing an upper portion of the substrate adjacent to the first dummy gate structure;

cleaning an inner surface defining the first trench;

forming a first epitaxial layer in the first trench; and

replacing the first and second dummy gate structures with first and second gate structures, respectively.

17. The method of claim 16, prior to nitriding the spacer layer, further comprising:

forming a first photoresist pattern on the substrate to cover the second region;

forming a first impurity region at an upper portion of the first region of the substrate using the first photoresist pattern as a mask;

removing the first photoresist pattern by an ashing process and/or a stripping process;

forming a second photoresist pattern on the substrate to cover the first region;

forming a second impurity region at an upper portion of the second region of the substrate using the second photoresist pattern as a mask; and

removing the second photoresist pattern by an ashing process and/or a stripping process.

18. The method of claim 17, wherein the spacer layer is formed of silicon nitride, and wherein removing the first photoresist pattern or removing the second photoresist pattern includes oxidizing the first spacer layer.

19. The method of claim 16, wherein the spacer layer is a first spacer layer, and

after nitriding the first spacer layer, further comprising:

forming a second spacer layer on the first spacer layer;

forming a third photoresist pattern on the substrate to cover the second region; and

anisotropically etching the first and second spacer layers to form first and second spacers sequentially stacked on a side surface of the first dummy gate structure.

20. The method of claim 19, after forming the first epitaxial layer, further comprising:

forming a fourth photoresist pattern on the substrate to cover the first region;

anisotropically etching the first and second spacer layers to form third and fourth spacers sequentially stacked on a side surface of the second dummy gate structure;

forming a second trench in the substrate by removing an upper portion of the substrate adjacent to the second dummy gate structure;

cleaning an interior surface defining the second trench; and

forming a second epitaxial layer in the second trench.

21-35. -35. (canceled)