DRIVE CIRCUIT AND SEMICONDUCTOR DEVICE

• US 20160036315A1
• Filed: 10/09/2015
• Published: 02/04/2016
• Est. Priority Date: 09/27/2013
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: OHASHI, Hidetomo, AKAHANE, Masashi
• Granted Patent: US 9,502,955 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 1/088 for the simultaneous control of series or parallel connected semiconductor devices
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/567 Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 2217/0063 High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load

Abstract

Malfunction can be reliably avoided even when a signal that drives a high side power device is not normally transmitted in a level shift circuit. In a drive circuit, a pulse generator circuit generates a set signal and reset signal that causes a high side power device to be turned on or off. The pulse generator circuit provides set and reset signals, via a level shift circuit, to a high side drive circuit. A high side potential (a high side reference potential or a high side power supply potential) is detected by a high side potential detector circuit. A high side potential determination circuit determines a change in potential that impedes the transmission of the set signal or reset signal in the level shift circuit, and causes the pulse generator circuit to regenerate the set signal or reset signal when the timing of the detection coincides with the timing at which the set signal or reset signal is generated.

Claims

1. A drive circuit, comprising:

a high side drive circuit that drives a high side power device;

a pulse generator circuit that generates

a set signal causing the high side power device to be turned on based on a first edge of a logic input signal, and

a reset signal causing the high side power device to be turned off based on a second edge of the logic input signal;

a level shift circuit that provides the set signal and reset signal to the high side drive circuit;

a high side potential detector circuit that detects high side potential; and

a high side potential determination circuit that provides an event signal based on a change in the high side potential detected by the high side potential detector circuit, wherein

the pulse generator circuit regenerates the reset signal based on the event signal provided by the high side potential determination circuit, and the logic input signal.

2. The drive circuit of claim 1, wherein

the pulse generator circuit regenerates the reset signal in response to the event signal being generated during an abnormal state of the drive circuit.

3. The drive circuit of claim 1, wherein

the event signal is output, with the first edge of the logic input signal as a trigger, based on a change in the high side potential in a first direction.

4. The drive circuit of claim 1, wherein

the high side potential is a high side reference potential or a high side power supply potential.

5. The drive circuit of claim 1, wherein

the high side potential detector circuit includes a resistant field plate having electrical field relaxation in a high side circuit high withstand voltage region.

6. The drive circuit of claim 1, wherein

the high side potential detector circuit includes a bipolar transistor configured to switch to an on-state or off-state in response to a change in the high side potential, the high side potential having a low side reference potential as a boundary.

7. The drive circuit of claim 1, wherein

the high side potential determination circuit is disposed on a low side reference potential side having ground potential as a reference.

8. The drive circuit of claim 1, wherein

the high side potential determination circuit includes at least one of

a first circuit that determines a malfunction of the level shift circuit based on the absolute value of the high side potential and

a second circuit that determines a malfunction of the level shift circuit based on the dV/dt of the high side potential.

9. The drive circuit of claim 8, wherein

the first circuit includes

a comparator that compares a potential corresponding to the high side potential detected by the high side potential detector circuit with a predetermined reference potential, and

an edge-triggered circuit that provides the event signal having a predetermined duration based on a first edge of an output signal of the comparator.

10. The drive circuit of claim 8, wherein

the first circuit includes

a comparator that compares a potential corresponding to the high side potential detected by the high side potential detector circuit with a predetermined reference potential,

a first edge-triggered circuit that provides a first event signal having a predetermined duration based on a first edge of an output signal of the comparator, and

a second edge-triggered circuit that provides a second event signal having a predetermined duration based on a first edge of a signal that is an inversion of the output signal of the comparator.

11. The drive circuit of claim 8, wherein

the second circuit includes

a capacitor that provides a changing potential corresponding to the high side potential detected by the high side potential detector circuit,

a first comparator that compares the changing potential corresponding to the high side potential provided via the capacitor with a predetermined first reference potential,

a second comparator that compares the changing potential corresponding to the high side potential provided via the capacitor with a predetermined second reference potential, and

a circuit that performs a logical operation on an output of the first comparator and an output of the second comparator, and

provides the event signal.

12. The drive circuit of claim 8, wherein

the second circuit includes

a capacitor that provides a changing potential corresponding to the high side potential detected by the high side potential detector circuit,

a first comparator that

compares the changing potential corresponding to the high side potential provided via the capacitor with a predetermined first reference potential and

provides a first event signal, and

a second comparator that

compares the changing potential corresponding to the high side potential provided via the capacitor with a predetermined second reference potential and

provides a second event signal.

13. The drive circuit of claim 1, wherein

the pulse generator circuit generates the set signal and reset signal based on the logic input signal, the logic input signal having priority over the generation of the set signal or reset signal, based on the event signal.

14. A semiconductor device comprising the drive circuit of claim 1.

15. The drive circuit of claim 1, wherein

the logic input signal is generated externally from the drive circuit.

16. The drive circuit of claim 5, wherein

a first node of the resistant field plate is connected to the high side potential,

a second node of the resistant field plate is connected to a low side reference potential, and

an intermediate node of the resistant field plate is an output terminal.

17. A drive circuit, comprising:

a high side drive circuit configured to drive a high side power device;

a pulse generator circuit configured to generate

a set signal causing the high side power device to be turned on based on a first edge of a logic input signal, and

a reset signal causing the high side power device to be turned off based on a second edge of the logic input signal;

a level shift circuit configured to provide the set signal and reset signal to the high side drive circuit;

a high side potential detector circuit configured to detect high side potential; and

a high side potential determination circuit configured to provide an event signal based on a change in the high side potential detected by the high side potential detector circuit,

wherein the pulse generator circuit is configured to regenerate the reset signal based on the event signal provided by the high side potential determination circuit, and the logic input signal.