DIGITALLY CONTROLLABLE POWER SOURCE

• US 20160036325A1
• Filed: 08/04/2015
• Published: 02/04/2016
• Est. Priority Date: 08/04/2014
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Van de Beek, Remco
• Granted Patent: US 9,798,338 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G05F 1/462 as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic

Abstract

Embodiments of power source circuits and methods for operating a power source circuit are described. In one embodiment, a method for operating a power source circuit involves receiving at the power source circuit at least one digital signal from a feedback loop and increasing or decreasing an output power signal of the power source circuit in response to the at least one digital signal. Other embodiments are also described.

Claims

1. A method for operating a power source circuit, the method comprising:

receiving at the power source circuit at least one digital signal from a feedback loop; and

increasing or decreasing an output power signal of the power source circuit in response to the at least one digital signal.

2. The method of claim 1, wherein the at least one digital signal comprises a digital activation signal and a digital control signal, wherein increasing or decreasing the output power signal of the power source circuit in response to the at least one digital signal comprises:

increasing or decreasing the output power signal during a rising edge of the digital activation signal based on the Boolean value of the digital control signal.

3. The method of claim 2, wherein increasing or decreasing the output power signal based on the Boolean value of the digital control signal during a rising edge of the digital activation signal comprises:

increasing the output power signal during the rising edge of the digital activation signal if the Boolean value of the digital control signal is 1; and

decreasing the output power signal during a rising edge of the digital activation signal if the Boolean value of the digital control signal is 0.

4. The method of claim 1, wherein increasing or decreasing the output power signal of the power source circuit in response to the at least one digital signal comprises:

causing an increase or a decrease in a voltage of a capacitor connected to a node between a first type of switching devices and a second type of switching devices in response to the at least one digital signal.

5. The method of claim 4, wherein the first type of switching devices comprise a plurality of PMOS transistors, and wherein the second type of switching devices comprise a plurality of NMOS transistors.

6. The method of claim 4, wherein causing the increase or the decrease in the voltage of the capacitor comprises:

activating and subsequently deactivating a first switching device; and

activating a second switching device, wherein the first and second switching devices are of the same type.

7. The method of claim 1, wherein the feedback loop is a direct current (DC) offset cancellation loop.

8. The method of claim 1, wherein the output power signal comprises an output current signal or an output voltage signal.

9. A power source circuit, the power source circuit comprising:

a digital controller configured to receive at least one digital signal from a feedback loop; and

a power signal generation circuit configured to increase or decrease an output power signal in response to the at least one digital signal.

10. The power source circuit of claim 9, wherein the at least one digital signal comprises a digital activation signal and a digital control signal, wherein the power signal generation circuit is further configured to:

increase or decrease the output power signal during a rising edge of the digital activation signal based on the Boolean value of the digital control signal.

11. The power source circuit of claim 10, wherein the power signal generation circuit is further configured to:

increase the output power signal during the rising edge of the digital activation signal if the Boolean value of the digital control signal is 1; and

decrease the output power signal during a rising edge of the digital activation signal if the Boolean value of the digital control signal is 0.

12. The power source circuit of claim 9, wherein the power signal generation circuit comprises:

a first type of switching devices;

a second type of switching devices; and

a capacitor connected to a node between the first type of switching devices and the second type of switching devices, wherein the digital controller is further configured to;

cause an increase or a decrease in a voltage of the capacitor in response to the at least one digital signal.

13. The power source circuit of claim 12, wherein the first type of switching devices comprise a plurality of PMOS transistors, and wherein the second type of switching devices comprise a plurality of NMOS transistors.

14. The power source circuit of claim 12, wherein the digital controller is further configured to:

activate and subsequently deactivate a first switching device of the power signal generation circuit; and

activate a second switching device of the power signal generation circuit, wherein the first and second switching devices are of the same type.

15. A direct current (DC) offset cancellation circuit, the DC offset cancellation circuit comprising:

an amplifier; and

the feedback loop of claim 9, wherein the feedback loop comprises;

the power source circuit of claim 9;

an analog-to-digital converter; and

a digital signal processor.

16. A current source circuit, the current source circuit comprising:

a digital controller configured to receive a digital activation signal and a digital control signal from a feedback loop; and

a current generation circuit configured to increase or decrease an output current during a rising edge of the digital activation signal based on the Boolean value of the digital control signal, wherein the current generation circuit comprises;

a first type of switching devices;

a second type of switching devices; and

a capacitor connected to a node between the first type of switching devices and the second type of switching devices.

17. The current source circuit of claim 16, wherein the first type of switching devices comprise a first PMOS transistor and a second PMOS transistor that are connected in series, and wherein the second type of switching devices comprise a first NMOS transistor that is connected to the capacitor at a gate terminal and a source terminal of the first NMOS transistor and a second NMOS transistor and a third NMOS transistor that are connected in series.

18. The current source circuit of claim 17, wherein the digital controller is further configured to:

cause an increase or a decrease in a voltage of the capacitor in response to the digital activation signal and the digital control signal.

19. The current source circuit of claim 16, wherein the digital controller comprises:

a plurality of inverters; and

a plurality of plural-input single-output non-sequential logic devices.

20. A direct current (DC) offset cancellation circuit, the DC offset cancellation circuit comprising:

an amplifier; and

the feedback loop of claim 16, wherein the feedback loop comprises;

the current source circuit of claim 16;

an analog-to-digital converter; and

a digital signal processor.