Periodic Signal Measurement Using Statistical Sampling

• US 20160041212A1
• Filed: 08/10/2015
• Published: 02/11/2016
• Est. Priority Date: 08/11/2014
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Darbinyan, Karen, Zorian, Yervant, Kumar, Arun, Mkhoyan, Mher
• Granted Patent: US 9,541,591 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 23/02 Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
• CPC Class Codes: G01R 29/0273 the pulse characteristic being duration, i.e. width (indicating that frequency of pulses is above or below a certain limit)
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371
• CPC Class Codes: G01R 31/31708 Analysis of signal quality G01R31/31901 takes precedence; measuring frequencies or analysing frequency spectra per se G01R23/00; measuring non-linear distortion per se G01R23/20
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G11C 2029/0401 in embedded memories
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters

Abstract

A fully-digital probabilistic measurement methodology in which a periodic signal generated on an IC device is sampled multiple times during a test period, with the asserted/de-asserted state of the periodic signal determined during each sampling event. A statistically significant number of sampling events are executed according to a reference signal frequency that is uncorrelated to the IC'"'"'s system clock, whereby each successive sampling event involves detecting an essentially random associated phase of the periodic signal such that the probability of detecting an asserted state during any given sampling event is proportional to the duty cycle of the periodic signal. A first count value records the number of sampling events in which the periodic signal is asserted, and a second count value records the total number of sampling events performed, whereby a ratio of these two count values provides a statistical measurement of the periodic signal'"'"'s duty cycle.

Claims

1. A method for performing analysis of a periodic signal having an associated duty cycle that is generated in accordance with operations of at least one of a functional circuit and an embedded memory circuit and, the method comprising:

performing multiple sampling events during a test period according to a sample timing schedule determined by repeatedly detecting a recurring signal feature of a reference signal, wherein each said sampling event includes determining an asserted/de-asserted state of an associated signal phase of said periodic signal occurring at an associated sample time determined by detecting an associated said recurring signal feature, and wherein the reference signal has a reference frequency that is uncorrelated to the periodic signal such that each recurring signal feature of said reference signal coincides in time with a substantially random signal phase of said periodic signal, whereby the probability of detecting an asserted state during any given sampling event is proportional to the duty cycle of the periodic signal;

generating a first count value such that said first count value only incrementally increases in response to each said sampling event occurring during said test period in which said periodic signal is in an asserted state; and

generating a second count value including a total number of said plurality of sampling events performed during said test period,

wherein performing said multiple sampling events comprises performing a statistically significant number of said sampling events during said test period such that a ratio of said first count value to said second count value at an end of said test period provides a statistically relevant measurement value of said duty cycle of the periodic signal.

2. The method of claim 1, further comprising generating said reference signal utilizing a reference signal generator circuit configured such that said reference frequency freely floats in accordance with changes in environment conditions of said reference signal generator circuit.

3. The method of claim 1, wherein generating said reference signal comprises utilizing a ring oscillator configured such that said reference frequency changes in accordance with a temperature of said ring oscillator.

4. The method of claim 1, wherein performing said plurality of sampling events comprises initiating each said sampling event upon detecting an associated edge of said reference signal.

5. The method of claim 1, further comprising at least one of storing said first count value and said second count value in memory that is co-disposed on a semiconductor substrate with said at least one of said functional circuit and said embedded memory circuit, and performing on-chip calculation of said ratio using calculating circuitry that is co-disposed on said semiconductor substrate with said at least one of said functional circuit and said embedded memory circuit.

6. The method of claim 5, further comprising utilizing said calculated ratio of said first count value to said second count value to perform at least one of a phase-locked loop (PLL) clock frequency measurement, an embedded memory delay measurement, a delay corner evaluation, and a process variation evaluation.

7. The method of claim 1, wherein performing said on-chip analysis comprises:

controlling said embedded memory circuit using a clock signal to generate a repetitive pulse signal by reading alternating “

1” and

“

0”

data bit values from memory cells of the memory circuit such that said repetitive pulse signal has a frequency determined by a memory access rate of the memory circuit;

generating a data time delay pulse signal using the repetitive pulse signal and the clock signal;

generating said first count value using said reference signal and said data time delay pulse signal; and

after said test period, calculating a data delay time from memory clock to memory output value using the first and second count values.

8. The method of claim 7, wherein controlling the embedded memory circuit to generate said repetitive pulse signal comprises:

writing a bit pattern into said embedded memory circuit such that each memory cell having an even-numbered memory address stores a “

0”

bit value, and each memory cell having an odd-numbered memory address stores a “

1”

bit value; and

reading the bit pattern from the memory circuit by operating the memory circuit in a continuous read operating mode.

9. The method of claim 7, wherein controlling the embedded memory circuit to generate said repetitive pulse signal comprises:

writing a “

0”

bit value into a first memory cell and a “

1”

bit value into a second memory cell; and

repeatedly alternately reading the first and second memory cells.

10. The method of claim 7, wherein generating the data time delay pulse signal comprises dividing the clock signal by two to generate a half-clock signal, and exclusive-ORing the repetitive pulse signal and the system half-clock signal to generate the data time delay pulse signal.

11. The method of claim 7, wherein calculating the data delay time from memory clock to memory output comprises multiplying the first count value with a period of said system clock signal, dividing by second count value, and then adding adding a clock divider flop delay time.

12. An integrated circuit (IC) device comprising:

at least one of a functional circuit and an embedded memory circuit fabricated on a semiconductor substrate and configured to operate in accordance with a system clock signal having a system clock frequency; and

a periodic signal measurement circuit fabricated on the semiconductor substrate and configured to analyze, during a test period, a periodic signal having an associated duty cycle and is generated in accordance with operations of said at least one of a functional circuit and an embedded memory circuit, said periodic signal measurement circuit including;

a reference signal generator configured to generate a reference signal such that a reference frequency of the reference signal is uncorrelated to the periodic signal;

a sampling circuit configured to repeatedly detect a recurring signal feature of said reference signal, and to perform multiple sampling events at respective sample times determined by sequential detections of said recurring signal feature, wherein each said sampling event includes determining an asserted/de-asserted state of an associated signal phase of said periodic signal occurring at an associated said sample time determined by the detection of an associated recurring signal feature such that the probability of detecting an asserted state during any given sampling event is proportional to the duty cycle of the periodic signal;

a detection counter configured to generate a first count value such that said first count value only incrementally increases in response to each said sampling event occurring during said test period in which said periodic signal is determined to be in an asserted state;

a sampling event counter configured to generate a second count value such that said second count value incrementally increases in response to every said sampling event occurring during said test period; and

a control circuit configured to control said detection counter and said sampling event counter such that a statistically significant number of said sampling events are performed during said test period such that a ratio of said first count value to said second count value at an end of said test period provides a statistically relevant measurement value of said duty cycle of the periodic signal.

13. The IC device of claim 12, wherein the reference signal generator is configured to generate said reference signal such that said reference frequency freely changes in accordance with changes in device operating environment conditions of said IC device.

14. The IC device of claim 13, wherein the reference signal generator comprises a ring oscillator configured such that reference frequency freely changes over time in response to changes in operating temperature of said ring oscillator.

15. The IC device of claim 12, wherein said sampling circuit comprises an edge detector configured to detect at least one of each rising edge and each falling edge of said reference signal, wherein said associated sample time of each said sampling event is determined by an associated said detected edge of said reference signal.

16. The IC device of claim 12, wherein said control circuit is configured to calculate at least one of a duty cycle, a frequency, and a pulse width of said periodic signal using said first count value to said second count value.

17. The IC device of claim 16,

wherein said functional circuit comprises a phase-locked loop (PLL) circuit configured to generate a PLL clock signal, and

wherein said periodic signal measurement circuit is configured to calculate said at least one of said duty cycle, said frequency, and said pulse width of said PLL clock signal.

18. The IC device of claim 12, further comprising means for controlling said embedded memory circuit such that said embedded memory circuit generates a repetitive pulse signal by reading alternating “

1” and

“

0”

data bit values from memory cells of said embedded memory circuit such that said repetitive pulse signal has a frequency determined by a memory access rate of the memory circuit,

wherein said periodic signal measurement circuit is configured to analyze said repetitive pulse signal.

19. The IC device of claim 18,

wherein the sampling circuit comprises:

a logic circuit configured to generate a data time delay pulse signal using the repetitive pulse signal and the system clock signal; and

a detection circuit configured to generate said first count value using said reference signal and said data time delay pulse signal,

wherein the periodic signal measurement circuit further comprises a calculation circuit configured to calculate a data delay time from memory clock to memory output value after said test period using the first and second count values.

20. A method for measuring a clock-to-output delay time of a memory read operation on a memory circuit initialized with bit patterns and controlled by a clock signal, comprising

reading the memory circuit such that the bit patterns generate a periodical pulse signal on an output terminal of the memory circuit,

exclusive ORing the periodic pulse signal and the clock signal to generate a clock-to-output pulse signal, and

measuring a pulse width of the generated clock-to-output pulse signal,

wherein the measured pulse width of the generated clock-to-output pulse signal indicates the clock-to-output delay time of the memory read operation.

21. The method in claim 20, wherein measuring the pulse width of the generated clock-to-output pulse signal further comprises:

sampling the generated pulse signal during a test period using a sample timing triggered by a recurring signal feature of a randomly generated reference signal, wherein each said sampling event includes determining an asserted/de-asserted state of said clock-to-output pulse signal, and

computing the pulse width of the clock-to-output pulse signal using a ratio of a number of said sampling events in which the clock-to-output pulse signal was asserted during said test period to a total number of sampling events occurring during said test period.

22. A circuit for measuring the clock-to-output delay time of a memory read operation on a memory circuit initialized with bit patterns and controlled by a memory read clock signal, comprising:

a first sub-circuit configured to read the memory circuit such that said bit patterns generate a repetitive pulse signal on an output terminal of the memory circuit,

a second sub-circuit configured to generate a clock-to-output pulse signal based on the repetitive pulse signal and the memory read clock signal, and

a third sub-circuit configured to measure at least one of a duty cycle and a pulse width of the clock-to-output pulse signal.

23. The circuit of claim 22, wherein the third sub-circuit comprises:

a reference signal generator configured to generate a reference signal having a reference frequency that is uncorrelated to the memory read clock signal during a test period;

a sampling circuit configured to perform multiple sampling events on said clock-to-output pulse signal during said test period, wherein each said sampling event includes determining an asserted/de-asserted state of said clock-to-output pulse signal at an associated sample time determined by a recurring signal feature of the reference signal; and

a control circuit configured to compute the pulse width of the clock-to-output pulse signal by calculating a ratio of a number of said sampling events in which the clock-to-output pulse signal was asserted during said test period to a total number of sampling events occurring during said test period.