SINGLE LAYER CAPACITIVE IMAGING SENSORS

• US 20160041654A1
• Filed: 10/20/2015
• Published: 02/11/2016
• Est. Priority Date: 01/12/2012
• Status: Active Grant

• Current Assignee: Synaptics Incorporated
• Original Assignee: Synaptics Incorporated
• Inventors: SOLVEN, Derek, REYNOLDS, Joseph Kurth, HOCH, David, DATTALO, Tracy Scott, BULEA, Mihai
• Granted Patent: US 9,817,533 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 2203/04112 Electrode mesh in capacitive digitiser: electrode for touch sensing is formed of a mesh of very fine, normally metallic, interconnected lines that are almost invisible to see. This provides a quite large but transparent electrode surface, without need for ITO or similar transparent conductive material
• CPC Class Codes: G06F 3/041 Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
• CPC Class Codes: G06F 3/04164 Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
• CPC Class Codes: G06F 3/0443 using a single layer of sensing electrodes
• CPC Class Codes: G06F 3/0448 Details of the electrode shape, e.g. for enhancing the detection of touches, for generating specific electric field shapes, for enhancing display quality

Abstract

Embodiments of the invention generally provide an input device that includes a plurality of sensing elements that are interconnected in desired way to acquire positional information of an input object, so that the acquired positional information can be used by other system components to control a display or other useful system components. One or more of the embodiments described herein, utilizes one or more of the techniques and sensor electrode array configuration disclosed herein to reduce or minimize the number of traces and/or electrodes required to sense the position of an input object within a sensing region of the input device.

Claims

1. A capacitive image sensor, comprising:

a plurality of sensor electrodes that are disposed within a sensing region, wherein the sensing region includes a plurality of unit cells of a sensing pattern, and wherein a subset of the plurality of sensor electrodes comprises;

a first sensor electrode disposed on a first surface of a substrate, the first sensor electrode having a first dimension and a second dimension substantially perpendicular to the first dimension, the first dimension being greater than the second dimension; and

two or more sensor electrodes of the subset of the plurality of sensor electrodes, the two or more sensor electrodes disposed adjacent to the first sensor electrode and on the first surface of the substrate, each of the two or more sensor electrodes being interdigitated with the first sensor electrode, wherein, within the sensing region, no jumper is coupled to any of the plurality of sensor electrodes.

2. The capacitive imaging sensor of claim 1, wherein each of the two or more sensor electrodes being interdigitated with the first sensor electrode comprises each of the two or more sensor electrodes overlapping the first sensor electrode in a direction that is substantially perpendicular to the first dimension.

3. The capacitive imaging sensor of claim 1, wherein each of the two or more sensor electrodes being interdigitated with the first sensor electrode comprises each of the two or more sensor electrodes overlapping the first sensor electrode in a direction that is substantially parallel to the first dimension.

4. The capacitive imaging sensor of claim 1, wherein the two or more sensor electrodes are disposed adjacent to one another along the first dimension.

5. The capacitive imaging sensor of claim 1, wherein each of the two or more sensor electrodes has recess regions in which interdigitation overlap occcurs.

6. The capacitive imaging sensor of claim 5, wherein the first sensor electrode includes a plurality of fingers which interdigitate with the two or more sensor electrodes in the recess regions.

7. The capacitive imaging sensor of claim 6, wherein the plurality of fingers are connected by a plurality of connecting segments, the plurality of connecting segments being continuous and alternating in a lengthwise direction.

8. The capacitive imaging sensor of claim 1, wherein the two or more sensor electrodes are disposed on opposite sides of the first sensor electrode.

9. The capacitive image sensor of claim 1, wherein the two or more sensor electrodes partially enclose the first sensor electrode.

10. A capacitive image sensor, comprising:

a first sensor electrode disposed on a first surface of a substrate, the first sensor electrode having a first dimension that is substantially perpendicular to, and longer than, a second dimension, the first sensor electrode having a first plurality of digits;

a second sensor electrode disposed on the first surface of the substrate, the second sensor electrode having a second plurality of digits that are interdigitated with the first plurality of digits in a first overlap area; and

a third sensor electrode disposed on the first surface of the substrate, the third sensor electrode having a third plurality of digits that are interdigitated with the first plurality of digits in a second overlap area that is different than the first overlap area, wherein the first sensor electrode, the second sensor electrode, and the third sensor electrode are independently routed.

11. The capacitive imaging sensor of claim 10, wherein the first plurality of digits, the second plurality of digits, and the third plurality of digits are longer in the first dimension.

12. The capacitive image sensor of claim 10, wherein the first plurality of digits, the second plurality of digits, and the third plurality of digits are longer in the second dimension.

13. The capacitive image sensor of claim 10, wherein the second sensor electrode is disposed adjacent to the third sensor electrode along the first dimension.

14. The capacitive image sensor of claim 10, wherein:

the second plurality of digits are interdigitated with the first plurality of digits in first recess regions of the second sensor electrode; and

the third plurality of digits are interdigitated with the first plurality of digits in second recess regions of the third sensor electrode.

15. The capacitive image sensor of claim 10, wherein the first plurality of digits are connected by a plurality of connecting segments, the plurality of connecting segments being continuous, angled, and alternating in angle in a lengthwise direction.

16. The capacitive image sensor of claim 10, wherein the second sensor electrode is disposed on an opposite side of the first sensor electrode as compared with the third sensor electrode.

17. The capacitive image sensor of claim 10, wherein the second sensor electrode and the third sensor electrode partially encloses the first sensor electrode.

18. A processing system, comprising:

a signal generating processor configured to drive one or more of a first sensor electrode, a second sensor electrode, and a third sensor electrode with a signal for capacitive sensing; and

a sensor processor configured to receive resulting signals with one or more of the first sensor electrode, the second sensor electrode, and the third sensor electrode, the resulting signals comprising effects related to the signal,

wherein the first sensor electrode is disposed on a first surface of a substrate of a capacitive image sensor, the first sensor electrode having a first dimension that is substantially perpendicular to, and longer than, a second dimension, the first sensor electrode having a first plurality of digits,

wherein the second sensor electrode is disposed on the first surface of the substrate, the second sensor electrode having a second plurality of digits that are interdigitated with the first plurality of digits in a first overlap area,

wherein the third sensor electrode is disposed on the first surface of the substrate, the third sensor electrode having a third plurality of digits that are interdigitated with the first plurality of digits in a second overlap area that is different than the first overlap area, and

wherein the first sensor electrode, the second sensor electrode, and the third sensor electrode are independently routed.

19. The processing system of claim 18, wherein the first plurality of digits, the second plurality of digits, and the third plurality of digits are longer in the first dimension.

20. The processing system of claim 18, wherein the first plurality of digits, the second plurality of digits, and the third plurality of digits are longer in the second dimension.