Failure Mapping in a Storage Array

• US 20160041878A1
• Filed: 08/07/2014
• Published: 02/11/2016
• Est. Priority Date: 08/07/2014
• Status: Active Grant

• Current Assignee: Pure Storage, Inc.
• Original Assignee: Pure Storage, Inc.
• Inventors: Davis, John D., Hayes, John, Tan, Zhangxi, Kannan, Hari, Miladinovic, Nenad
• Granted Patent: US 9,558,069 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 11/142 Reconfiguring to eliminate the error group management mechanisms in a peer-to-peer network H04L67/1044
• CPC Class Codes: G06F 11/1423 by reconfiguration of paths
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2201/805 Real-time
• CPC Class Codes: G06F 2201/82 Solving problems relating to consistency
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/202 Non-volatile memory
• CPC Class Codes: G06F 2212/466 Metadata, control data
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/36 Data generation devices, e.g. data inverters
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/44 : Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/76 : using address translation or modifications
• CPC Class Codes: G11C 29/765 : in solid state disks

Abstract

A storage cluster is provided. The storage cluster includes a plurality of storage nodes within a chassis. The plurality of storage nodes has flash memory for storage of user data and is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the storage nodes can access the user data with a failure of two of the plurality of storage nodes. Each of the storage nodes is configured to generate at least one address translation table that maps around defects in the flash memory on one of a per flash package basis, per flash die basis, per flash plane basis, per flash block basis, per flash page basis, or per physical address basis. Each of the plurality of storage nodes is configured to apply the at least one address translation table to write and read accesses of the user data.

Claims

1. A method of failure mapping, comprising:

distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes as a storage cluster, wherein each of the plurality of storage nodes has a non-volatile solid-state storage with flash memory and wherein the user data is accessible via the erasure coding from a remainder of the plurality of storage nodes in event of two of the plurality of storage nodes being unreachable;

mapping physical addresses of defects in the flash memory, on a basis of one of per flash package, per flash die, per flash plane, per flash block, per flash page, or per physical memory address; and

mapping around the defects in the flash memory during accesses to the user data, wherein a processor performs at least one method operation.

2. The method of claim 1, wherein mapping the physical addresses of defects in the flash memory includes generating a defects map of a physical address space of a flash memory, the defects map indicating the physical addresses of the defects in the flash memory.

3. The method of claim 1, further comprising:

generating an address translation table that maps a memory address space to a physical address space according to the mapping the physical addresses of the defects in the flash memory, such that the address translation table maps around the defects in the flash memory, wherein mapping around the defects in the flash memory during the accesses to the user data is via application of the address translation table and is expandable without limit.

4. The method of claim 1, wherein:

the flash memory includes a plurality of flash dies;

at least one flash die with a defect known at a time of assembly of the storage cluster is included in the plurality of flash dies; and

mapping the physical addresses of the defects in the flash memory includes mapping the defect known at the time of assembly of the storage cluster.

5. The method of claim 1, wherein mapping around the defects in the flash memory includes mapping around at least one of:

a defective physical address in the flash memory, a defective flash plane, a defective flash block, a defective flash die, or a defective flash package.

6. The method of claim 1, further comprising:

detecting, during operation of the storage cluster, a defect in one of;

a flash plane, a flash block, a flash die, a flash package, or a bit in flash memory, wherein mapping the physical addresses of defects in the flash memory includes mapping the defect.

7. The method of claim 1, wherein mapping around the defects in the flash memory includes translating memory addresses in a memory space to usable physical addresses in a physical address space, with the usable physical addresses in the physical address space excluding the physical addresses of the defects in the flash memory.

8. A plurality of storage nodes in a chassis, comprising:

the plurality of storage nodes configured to communicate together as a storage cluster, each of the plurality of storage nodes having flash memory for user data storage, the plurality of storage nodes configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes such that the plurality of storage nodes maintain ability to read the user data, using erasure coding, despite a loss of two of the plurality of storage nodes;

each of the plurality of storage nodes configured to determine usable physical addresses in the flash memory and unusable physical addresses in the flash memory at a level of one of a flash package, a flash die, a flash plane, a flash block, a flash page, or a bit, based on defects in the flash memory; and

each of the plurality of storage nodes configured to map accesses to the user data to the usable physical addresses in the flash memory, such that the accesses to the user data bypass the unusable physical addresses in the flash memory.

9. The plurality of storage nodes of claim 8, further comprising:

the plurality of storage nodes configured to receive externally-provided information from one of a manufacturer of flash packages, a manufacturer of flash dies, testing of flash packages, testing of flash dies, or testing of the flash memory, wherein the each of the plurality of storage nodes configured to determine the usable physical addresses and the unusable physical addresses is based at least in part on the externally-provided information.

10. The plurality of storage nodes of claim 8, further comprising:

each of the plurality of storage nodes configured to detect a defect in the flash memory and to determine at least one unusable physical address therefrom, wherein the unusable physical addresses in the flash memory include the at least one unusable physical address.

11. The plurality of storage nodes of claim 8, wherein the usable physical addresses in the flash memory map around the unusable physical addresses in the flash memory and wherein the unusable physical addresses in the flash memory map the defects in the flash memory in a physical address space.

12. The plurality of storage nodes of claim 8, further comprising:

each of the plurality of storage nodes configured to generate a defects map that indicates the unusable physical addresses in the flash memory.

13. The plurality of storage nodes of claim 8, further comprising:

each of the plurality of storage nodes configured to generate at least one address translation table that references the usable physical addresses in the flash memory and excludes the unusable physical addresses in the flash memory.

14. The plurality of storage nodes of claim 8, further comprising:

the plurality of storage nodes configured to support a graceful degradation of storage capacity in event of a failure of at least a portion of a flash die.

15. A storage cluster, comprising:

a plurality of storage nodes within a chassis, each of the plurality of storage nodes having flash memory for storage of user data, the plurality of storage nodes configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes such that the plurality of storage nodes can access the user data, via erasure coding, with a failure of two of the plurality of storage nodes;

each of the plurality of storage nodes configured to generate at least one address translation table that maps around defects in the flash memory on one of a per flash package basis, per flash die basis, per flash plane basis, per flash block basis, per flash page basis, or per physical address basis; and

each of the plurality of storage nodes configured to apply the at least one address translation table to write and read accesses of the user data.

16. The storage cluster of claim 15, wherein:

the flash memory of one of the plurality of storage nodes includes as a known defect one of;

a known defective flash package, a known defective flash die, a known defective flash plane, a known defective flash block, a known defective flash page, or a known defective bit; and

the at least one address translation table maps around the known defect.

17. The storage cluster of claim 15, further comprising:

each of the plurality of storage nodes configured to perform and track error correction; and

each of the plurality of storage nodes configured to determine the defects in the flash memory based at least in part on the error correction as tracked.

18. The storage cluster of claim 15, wherein:

the flash memory of at least one of the plurality of storage nodes includes at least one flash die that is downgraded as a result of testing and has a known defect.

19. The storage cluster of claim 15, further comprising:

each of the plurality of storage nodes configured to generate a defects map that indicates the defects in the flash memory.

20. The storage cluster of claim 15, further comprising:

the plurality of storage nodes configured to support yield recovery of a flash package having a plurality of flash dies including at least one defective flash die and yield recovery of a flash die having a plurality of defective flash blocks.