METHODS TO ENHANCE EFFECTIVE WORK FUNCTION OF MID-GAP METAL BY INCORPORATING OXYGEN AND HYDROGEN AT A LOW THERMAL BUDGET

• US 20160042953A1
• Filed: 10/26/2015
• Published: 02/11/2016
• Est. Priority Date: 11/21/2008
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Niimi, Hiroaki, Chambers, James Joseph
• Granted Patent: US 9,721,796 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02244 of a metallic layer
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A process is disclosed of forming metal replacement gates for PMOS transistors with oxygen in the metal gates such that the PMOS gates have effective work functions above 4.85. Metal work function layers in the PMOS gates are oxidized at low temperature to increase their effective work functions to the desired PMOS range. Hydrogen may also be incorporated at an interface between the metal gates and underlying gate dielectrics. Materials for the metal work function layers and processes for the low temperature oxidation are disclosed.

Claims

1. A method of forming an integrated circuit comprising:

forming a PMOS gate dielectric layer on a substrate;

forming a PMOS gate work function metal layer on the PMOS gate dielectric layer, such that;

said PMOS gate work function metal layer includes oxygen atoms such that said oxygen atoms have a distribution of at least 1×

10¹⁵ atoms/cm² within 1 nanometer of a top surface of said PMOS gate dielectric layer; and

said PMOS gate work function metal layer includes oxygen such that an effective work function of said PMOS gate work function metal layer is above 4.85 eV; and

forming a PMOS metal fill gate over and in direct electrical connection with said PMOS gate work function metal layer.

2. The method of claim 1, wherein said PMOS gate work function metal layer is between 1 and 10 nanometers thick.

3. The method of claim 1, wherein said PMOS gate work function metal layer includes a metal selected from the group consisting of:

TiN, TaN, and TaC.

4. The method of claim 1, wherein said PMOS gate work function metal layer includes hydrogen atoms, deuterium atoms or a combination thereof, such that said hydrogen and deuterium atoms have a distribution of at least 1×

10¹⁵ atoms/cm² within 1 nanometer of said top surface of said PMOS gate dielectric layer.

5. The method of claim 1, wherein a composition of said PMOS gate dielectric layer is selected from the group consisting of:

SiO₂, SiON, Al₂O₃, AlON, HfO, HfSiO, HfSiON, ZrO, ZrSiO, ZrSiON, nitridated SiO₂, nitridated Al₂O₃, nitridated HfO, nitridated HfSiO, nitridated ZrO, nitridated ZrSiO, and any combination thereof.

6. A process of forming an integrated circuit, comprising the steps of:

forming a gate dielectric layer on a substrate;

forming a metal layer on the gate dielectric layer, such that said metal layer has an effective work function between 4.5 and 4.7 eV;

forming a dummy gate layer on the metal layer;

forming a gate photoresist pattern over said dummy gate layer, such that said gate photoresist pattern defines an area for a PMOS gate of a PMOS transistor;

using the gate photoresist pattern, removing said dummy gate layer, said metal layer and said gate dielectric layer outside of said area for said PMOS gate;

forming a fill oxide layer over the substrate including over the dummy gate layer;

removing said fill oxide layer from said PMOS gate area over said dummy gate layer;

removing said dummy gate layer in said areas for said PMOS gate;

performing a low temperature oxidation process on said metal layer to form a PMOS gate work function metal layer, such that said effective work function of the metal layer is increased to a value above 4.85 eV; and

forming a metal fill gate layer over said PMOS gate work function metal layer.

7. The process of claim 6, wherein:

said PMOS gate work function metal layer is between 1 and 10 nanometers thick; and

said PMOS gate work function metal layer includes a metal selected from the group consisting of;

TiN, TaN, and TaC.

8. The process of claim 6, wherein said step of performing a low temperature oxidation process further includes the step of exposing said metal layer to a steam ambient up to one atmosphere in pressure between 300°

C. and 600°

C. for 10 seconds to 30 minutes.

9. The process of claim 6, wherein said step of performing a low temperature oxidation process further includes exposing said metal layer to a plasma containing oxygen and hydrogen, by a process including:

placing said integrated circuit in a plasma chamber;

introducing oxygen gas into said plasma chamber at a flow rate of between 1 and 250 sccm;

introducing hydrogen gas into said plasma chamber at a flow rate of between 1 and 20 sccm;

maintaining a pressure in said plasma chamber between 0.1 and 5 torr;

providing between 1500 and 5000 watts of microwave power is provided to said oxygen gas and said hydrogen gas in said plasma chamber; and

maintaining a temperature of said integrated circuit in said plasma chamber between 25°

C. and 500°

C.

10. The process of claim 6, wherein said step of performing a low temperature oxidation process further includes the steps of:

exposing said metal layer to a plasma containing oxygen, by a process including;

placing said integrated circuit in a first plasma chamber;

introducing oxygen gas into said first plasma chamber at a flow rate of between 5 and 50 sccm;

maintaining a pressure in said first plasma chamber between 50 and 150 millitorr;

providing between 500 and 1500 watts of microwave power is provided to said oxygen gas and said hydrogen gas in said first plasma chamber; and

maintaining a temperature of said integrated circuit in said first plasma chamber between 25°

C. and 400°

C.; and

exposing said metal layer to a plasma containing hydrogen, by a process including;

placing said integrated circuit in a second plasma chamber;

introducing hydrogen gas into said second plasma chamber at a flow rate of between 5 and 20 sccm;

maintaining a pressure in said second plasma chamber between 250 and 500 millitorr;

providing between 500 and 1500 watts of microwave power is provided to said oxygen gas and said hydrogen gas in said second plasma chamber; and

maintaining a temperature of said integrated circuit in said second plasma chamber between 25°

C. and 500°

C.

11. The process of claim 6, wherein said step of performing a low temperature oxidation process further includes the step of exposing said metal layer to an electrolyte solution containing ionized oxygen radicals and hydrogen ions, in which a composition of said electrolyte solution is selected from the group consisting of:

water, an alcohol, an aldehyde, an amide, a carboxylic acid, an ether, a peroxide, a ketone, an alkaline chemical, and any combination thereof.

12. The process of claim 6, wherein said PMOS gate work function metal layer includes oxygen atoms such that said oxygen atoms have a distribution of at least 1×

10¹⁵ atoms/cm² within 1 nanometer of a top surface of said gate dielectric layer.

13. The process of claim 6, wherein said PMOS gate work function metal layer includes oxygen atoms such that said oxygen atoms have an average concentration between 1×

10¹⁸ atoms/cm³ and 1×

10²¹ atoms/cm³.

14. The process of claim 6, wherein said PMOS gate work function metal layer includes hydrogen atoms, deuterium atoms or a combination thereof, such that said hydrogen and deuterium atoms have a distribution of at least 1×

10¹⁵ atoms/cm² within 1 nanometer of a top surface of said gate dielectric layer.