METHOD OF REMOVING OXIDE ON SEMICONDUCTOR SURFACE BY LAYER OF SULFUR

• US 20160042966A1
• Filed: 08/07/2014
• Published: 02/11/2016
• Est. Priority Date: 08/07/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: KELLY, Andrew Joseph, ONIKI, Yusuke
• Granted Patent: US 9,412,605 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02057 Cleaning during device manufacture
• CPC Class Codes: H01L 21/0206 during, before or after processing of insulating layers
• CPC Class Codes: H01L 21/02301 in-situ cleaning
• CPC Class Codes: H01L 21/02658 Pretreatments cleaning in general H01L21/02041
• CPC Class Codes: H01L 21/28255 the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
• CPC Class Codes: H01L 21/28264 the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/30621 Vapour phase etching
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31122 of layers not containing Si, e.g. PZT, Al2O3
• CPC Class Codes: H01L 21/31604 Deposition from a gas or vapour H01L21/31691, H01L21/31695 take precedence
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

Embodiments of the present disclosure relate generally to a method of passivating and/or removing oxides on a semiconductor surface by using ammonium sulfide, the ammonium sulfide is formed by reacting ammonia and hydrogen sulfide in a semiconductor processing chamber, therefore the ammonium sulfide can be used to clean and remove oxides on a semiconductor surface without the concern of ESH and storage, the ammonium sulfide can also be used to passivate a semiconductor surface by forming a layer of sulfur, and thus preventing the reformation of native oxides, the layer of sulfur can be optionally removed to reduce the thickness of the semiconductor material.

Claims

1. A method for removing an oxide on a semiconductor material comprising:

providing ammonia and hydrogen sulfide on a semiconductor surface overlaid with an oxide;

reacting the ammonia with the hydrogen sulfide to form an ammonium sulfide; and

removing the oxide on the semiconductor surface by the ammonium sulfide.

2. The method of claim 1, further comprising passivating the semiconductor surface by reacting ammonia with hydrogen sulfide to form a layer of sulfur with the semiconductor surface.

3. The method of claim 1, wherein the semiconductor surface is a surface of a channel region of a gate-all-around vertical nanowire of a field effect transistor.

4. The method of claim 1, wherein the ammonia, the hydrogen sulfide and the ammonium sulfide are in gas phase.

5. The method of claim 1, wherein the molar ratio of the ammonia to the hydrogen sulfide is 1:

1 to 2;

1.

6. The method of claim 1, wherein the semiconductor surface is a surface of a Ge or III-V semiconductor.

7. The method of claim 6, wherein the oxide on the semiconductor material is a native oxide of the Ge or III-V semiconductor.

8. A method for passivating a semiconductor material comprising:

providing ammonia and hydrogen sulfide on a semiconductor surface; and

reacting the ammonia with the hydrogen sulfide to form a layer of sulfur on the semiconductor surface as a passivation layer over the semiconductor surface.

9. The method of claim 8, wherein the semiconductor surface is a surface of a Ge or III-V semiconductor.

10. The method of claim 8, wherein the semiconductor surface is a surface of a channel region of a gate-all-around vertical nanowire of a field effect transistor.

11. The method of claim 8, wherein the ammonia and the hydrogen sulfide are in gas phase.

12. The method of claim 8, wherein the molar ratio of the ammonia to the hydrogen sulfide is 1:

1 to 2;

1.

13. A method for reducing the thickness of a semiconductor material comprising:

providing ammonia and hydrogen sulfide on a semiconductor surface of a semiconductor material;

reacting the ammonia with the hydrogen sulfide to form a layer of sulfur on the semiconductor surface; and

removing the layer of sulfur and thereby reducing the thickness of the semiconductor material.

14. The method of claim 13, further comprising repeating the forming and removing of the layer of sulfur a plurality of time to obtain a predefined semiconductor material thickness.

15. The method of claim 13, further comprising forming another layer of sulfur with the semiconductor surface as a passivation layer over the semiconductor material after reducing the thickness of the semiconductor material.

16. The method of claim 13, wherein the layer of sulfur is removed by conducting an annealing.

17. The method of claim 13, wherein the semiconductor material is Ge or III-V semiconductor.

18. The method of claim 13, wherein the semiconductor surface is the surface of a channel region of a gate-all-around vertical nanowire of a field effect transistor.

19. The method of claim 13, wherein the ammonia and the hydrogen sulfide are in gas phase.

20. The method of claim 13, wherein the molar ratio of the ammonia to the hydrogen sulfide is 1:

1 to 2;

1.