RAISED METAL SEMICONDUCTOR ALLOY FOR SELF-ALIGNED MIDDLE-OF-LINE CONTACT

• US 20160043075A1
• Filed: 08/07/2014
• Published: 02/11/2016
• Est. Priority Date: 08/07/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lavoie, Christian, Leobandung, Effendi
• Granted Patent: US 9,754,935 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/28525 the conductive layers comprising semiconducting material H01L21/28518, H01L21/28537 take precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/53271 containing semiconductor material, e.g. polysilicon
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method to form self-aligned middle-of-line (MOL) contacts between functional gate structures without the need of lithographic patterning and etching by using raised metal semiconductor alloy regions is provided. Raised metal semiconductor alloy regions are formed by reacting a metal layer with a semiconductor material in raised semiconductor material regions formed on portions of at least one active region of a substrate located between functional gate structures. The metal layer includes a metal capable of forming a metal semiconductor alloy with a large volume expansion such that the resulting metal semiconductor alloy regions can be raised to a same height as that of the functional gate structures. As a result, no lithographic patterning and etching between functional gate structures are needed when forming MOL contacts to these raised metal semiconductor alloy regions.

Claims

1. A semiconductor structure comprising:

a plurality of functional gate structures located over at least one active region of a substrate;

a plurality of planar source/drain regions, each of the plurality of planar source/drain region positioned in a portion of the at least one active region located between adjacent functional gate structures of the plurality of functional gate structures;

a plurality of raised source/drain regions, each of the plurality of raised source/drain regions overlying a corresponding planar source/drain region of the plurality of planar source/drain regions; and

a plurality of metal semiconductor alloy regions, each of the plurality of metal semiconductor alloy regions overlying a corresponding raised source/drain region of the plurality of raised source/drain regions and having a top surface substantially coplanar with topmost surfaces of the plurality of functional gate structures.

2. The semiconductor structure of claim 1, wherein the plurality of raise source/drain regions comprises a silicon-containing semiconductor material or a germanium-containing semiconductor material.

3. The semiconductor structure of claim 1, wherein the plurality of metal semiconductor alloy regions comprises a metal silicide or a metal germicide.

4. The semiconductor structure of claim 3, wherein the metal silicide comprises platinum silicide, palladium silicide, or lanthanum silicide, and wherein the metal germicide comprises platinum germicide, palladium germicide, or lanthanum germicide.

5. The semiconductor structure of claim 1, wherein each of the functional gate structures comprises a stack of a gate electric, a gate electrode, and a gate cap.

6. The semiconductor structure of claim 5, further comprising a plurality of source/drain contact structures extending through at least one contact level dielectric layer and in contact with the plurality of metal semiconductor alloy regions, and a plurality of gate contact structures extending through the at least one contact level dielectric layer and the gate cap in each of the plurality of functional gate structures and in contact with the gate electrode in each of the plurality of functional gate structures.

20. The method of claim 6, wherein the forming the plurality of sacrificial gate structures over the at least one active region of the substrate comprises:

forming a material stack of a sacrificial gate dielectric layer on the at least one active region of the substrate, a sacrificial gate conductor layer on the sacrificial gate dielectric layer and a sacrificial gate cap layer on the sacrificial gate conductor layer; and

patterning the material stack.

7. A method of forming a semiconductor structure comprising:

forming a plurality of sacrificial gate structures over at least one active region of a substrate;

forming a gate spacer on each sidewall of the plurality of sacrificial gate structures;

forming a plurality of raised semiconductor material regions over portions of the at least one active region between adjacent sacrificial gate structures of the plurality of sacrificial gate structures;

forming a interlevel dielectric (ILD) layer over the substrate, the ILD layer covering the plurality of raised semiconductor material regions and having a top surface coplanar with topmost surfaces of the plurality of sacrificial gate structures;

replacing each of the plurality of sacrificial gate structures with a functional gate structure to provide a plurality of functional gate structures;

recessing the ILD layer to expose the plurality of raised semiconductor material regions;

forming a metal layer over the substrate to cover the plurality of raised semiconductor material regions, the metal layer having a top surface above topmost surfaces of the plurality of functional gate structures; and

forming a metal semiconductor alloy region on each of remaining portions of the plurality of raised semiconductor material regions to provide a plurality of metal semiconductor alloy regions, the plurality of metal semiconductor alloy having top surfaces substantially coplanar with the topmost surfaces of the plurality of functional gate structures.

8. The method of claim 7, wherein the metal layer comprises a metal that has a large volume expansion upon reaction with a semiconductor material of the plurality of raised semiconductor material regions.

9. The method of claim 8, wherein the metal layer comprises platinum, palladium or lanthanum, and wherein the plurality of raised semiconductor material regions comprises a silicon-containing semiconductor material or a germanium-containing semiconductor material.

10. The method of claim 9, wherein the forming the plurality of metal semiconductor alloy regions comprises performing an anneal to react a metal in the metal layer with the silicon-containing semiconductor material or the germanium-containing semiconductor material in the plurality of raised semiconductor material regions.

11. The method of claim 7, further comprising removing an unreacted portion of the metal layer from the substrate, the plurality of metal semiconductor alloy regions and the plurality of functional gate structures.

12. The method of claim 7, further comprising forming a plurality of planar source/drain regions in the portions of the at least one active region between the adjacent sacrificial gate structures of the plurality of sacrificial gate structures.

13. The method of claim 12, wherein the forming the plurality of planar source/drain regions comprises implanting a first type of dopants into the portions of the at least one active region between adjacent sacrificial gate structures of the plurality of sacrificial gate structures.

14. The method of claim 13, wherein the forming the plurality of raised semiconductor material regions comprises epitaxially depositing a semiconductor material on top surfaces of the plurality of planar source/drain regions and doping the semiconductor material with dopants.

15. The method of claim 7, wherein the replacing each of the plurality of sacrificial gate structures with the functional gate structure comprises:

removing the plurality of sacrificial gate structures to provide gate cavities, each of the gate cavities is laterally surrounded by the gate spacers;

forming a gate dielectric on a bottom surface and sidewalls of each of the gate cavities;

forming a gate electrode over the gate dielectric in each of the gate cavities, the gate electrode having a top surface coplanar with topmost surfaces of the gate dielectric; and

forming a gate cap over the gate dielectric and the gate electrode in each of the gate cavities, the gate cap having a top surface coplanar with the top surface of the ILD layer.

16. The method of claim 7, further comprising forming at least one contact level dielectric layer over the recessed ILD layer, the plurality of functional gate structures and the plurality of metal semiconductor alloy regions, wherein the at least one contact level dielectric layer has a topmost surface above the topmost surfaces of the plurality of functional gate structures and the plurality of metal semiconductor alloy regions.

17. The method of claim 16, wherein the at least one contact level dielectric layer comprises a stack of a first contact level dielectric layer, an etch stop layer and a second contact level dielectric layer.

18. The method of claim 17, further comprising forming a source/drain via hole extending through the at least one contact level dielectric layer to expose a corresponding metal semiconductor alloy region, and a gate via hole extending through the at least one contact level dielectric layer and a gate cap of a corresponding functional gate structure of the plurality of functional gate structures to expose a gate electrode of the corresponding functional gate structure.

19. The method of claim 18, further comprising filling source/drain via holes to form source/drain contacts and gate via holes to form gate contact with a conductive metal.