Semiconductor Device And Fabricating The Same

• US 20160043085A1
• Filed: 10/20/2015
• Published: 02/11/2016
• Est. Priority Date: 08/01/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Hsu, Ting-Hung
• Granted Patent: US 9,443,856 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

The present disclosure provides a method for fabricating an integrated circuit device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, and source/drain regions respectively. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the first gate region to form first outer oxide layer and inner nanowire set, and exposing the first inner nanowire set. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire set. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the second gate region to form second outer oxide layer and inner nanowire set, and exposing the second inner nanowire set. A second HK/MG stack wraps around the second inner nanowire set.

Claims

1. An integrated circuit device comprising:

a substrate having an N-type metal-oxide-semiconductor (NMOS) region and a P-type metal-oxide-semiconductor (PMOS) region;

a first gate region and a first source feature separated from a corresponding first drain feature by the first gate region in the NMOS region; and

a second gate region and a second source feature separated from a corresponding second drain feature by the second gate region in the PMOS region,

wherein the first gate region includes a plurality of first nanowire sets having a first semiconductor material, the first nanowire sets extending from the first source feature to the corresponding first drain feature,

wherein the second gate region includes a plurality of second nanowire sets having a second semiconductor material, the second nanowire sets extending from the second source feature to the corresponding second drain feature, and

wherein each of the NMOS region and PMOS region includes at least one intra-isolation region between nanowire sets and at least one inter-isolation region at one side of each of the NMOS region and PMOS region, wherein a depth of the inter-isolation region is greater than a depth of the intra-isolation region.

2. The device of claim 1, wherein the first semiconductor material includes Si.

3. The device of claim 1, wherein the second semiconductor material includes SiGe.

4. The device of claim 1, further comprising:

a first anti-punch through (APT) region formed below the first nanowire sets, the first APT implanted with p-type dopants; and

a second APT region formed below the second nanowire sets, the second APT implanted with n-type dopants.

5. The device of claim 1, wherein the depth of the intra-isolation is in the range of about 40 nm to about 60 nm.

6. The device of claim 1, wherein the depth of the inter-isolation is in the range of about 60 nm to about 120 nm.

7. The device of claim 1, further comprising an anti-punch through feature disposed in the substrate directly under one of the first nanowire sets from the plurality of first nanowire sets.

8. A device comprising:

a first nanowire extending from a first source/drain feature to a second source/drain feature;

a first gate dielectric layer wrapping around the first nanowire;

a second nanowire extending from the first source/drain feature to the second source/drain feature;

a second gate dielectric layer wrapping around the second nanowire;

a metal gate electrode wrapping around the first and second gate dielectric layers and extending from the first gate dielectric layer to the second gate dielectric layer;

a first dielectric isolation feature disposed in a substrate between the first and second nanowires and extending to a first depth within the substrate; and

a second dielectric isolation feature disposed in the substrate adjacent the first nanowire and extending to a second depth within the substrate, the second depth being different than the first depth.

9. The device of claim 8, wherein the first nanowire is formed of Si.

10. The device of claim 8 wherein the first nanowire is formed of Ge.

11. The device of claim 8, further comprising a first anti-punch through feature disposed in the substrate directly under the first nanowire, and

wherein the first anti-punch through feature extends continuously from the first dielectric isolation feature to the second dielectric isolation feature.

12. The device of claim 11, further comprising:

a third dielectric isolation feature disposed in the substrate adjacent the second nanowire and extending to the second depth within the substrate; and

a second anti-punch through feature disposed in the substrate directly under the second nanowire, wherein the second anti-punch through feature extends continuously from the third dielectric isolation feature to the first dielectric isolation feature.

13. The device of claim 11, further comprising a sidewall spacer extending along a sidewall of the first anti-punch through feature.

14. The device of claim 8, further comprising an interlayer dielectric layer disposed over the first source/drain feature and having a top surface facing away from the substrate, and

wherein a top surface of the metal gate electrode is substantially coplanar with the top surface of the interlayer dielectric layer.

15. A device comprising:

a first nanowire extending from a first source/drain feature to a second source/drain feature, wherein the first nanowire is formed of a first material that includes germanium;

a first gate dielectric layer wrapping around the first nanowire;

a second nanowire extending from a third source/drain feature to a fourth source/drain feature, wherein the second nanowire is formed of a second material that includes silicon, the second material being different than the first material;

a second gate dielectric layer wrapping around the second nanowire;

a first metal gate electrode wrapping around the first dielectric layer;

a second metal gate electrode wrapping around the second dielectric layer;

a first dielectric isolation feature disposed in a substrate between the first and second nanowires and extending to a first depth within the substrate; and

a second dielectric isolation feature disposed in the substrate between the first and second nanowires and extending to a second depth within the substrate, the second depth being different than the first depth.

16. The device of claim 15, further comprising:

a third nanowire extending from the first source/drain feature to the second source/drain feature, wherein the third nanowire is formed of the first material that includes germanium; and

a third gate dielectric layer wrapping around the third nanowire, and

wherein the first metal gate electrode wraps around the third gate dielectric layer and extends continuously from the first gate dielectric layer to the third gate dielectric layer.

17. The device of claim 15, further comprising:

a third nanowire extending from the third source/drain feature to the fourth source/drain feature, wherein the third nanowire is formed of the second material that includes silicon; and

a third gate dielectric layer wrapping around the third nanowire, and

wherein the second metal gate electrode wraps around the third gate dielectric layer and extends continuously from the second gate dielectric layer to the third gate dielectric layer.

18. The device of claim 15, further comprising a third dielectric isolation feature disposed in the substrate adjacent the first nanowire and extending to the first depth within the substrate;

and

a first anti-punch through feature disposed in the substrate directly under the first nanowire, wherein the first anti-punch through feature extends continuously from the first dielectric isolation feature to the third dielectric isolation feature.

19. The device of claim 18, further comprising a sidewall spacer extending along a sidewall of the first anti-punch through feature.

20. The device of claim 18, further comprising an interlayer dielectric layer disposed over the first source/drain feature, and

wherein a top surface of the first metal gate electrode is not covered by the interlayer dielectric layer.