Split-Gate Flash Memory Cell With Improved Scaling Using Enhanced Lateral Control Gate To Floating Gate Coupling

• US 20160043095A1
• Filed: 07/02/2015
• Published: 02/11/2016
• Est. Priority Date: 08/08/2014
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Yang, Jeng-Wei, Su, Chien-Sheng, Do, Nhan, Wu, Man-Tang, Chen, Chun-Ming
• Granted Patent: US 10,312,246 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A non-volatile memory cell includes a semiconductor substrate of first conductivity type, first and second spaced-apart regions in the substrate of second conductivity type, with a channel region in the substrate therebetween. A floating gate has a first portion disposed vertically over a first portion of the channel region, and a second portion disposed vertically over the first region. The floating gate includes a sloping upper surface that terminates with one or more sharp edges. An erase gate is disposed vertically over the floating gate with the one or more sharp edges facing the erase gate. A control gate has a first portion disposed laterally adjacent to the floating gate, and vertically over the first region. A select gate has a first portion disposed vertically over a second portion of the channel region, and laterally adjacent to the floating gate.

Claims

1. A non-volatile memory cell, comprising:

a substrate of semiconductor material of a first conductivity type;

first and second spaced-apart regions in the substrate of a second conductivity type different from the first conductivity type, with a channel region in the substrate therebetween;

an electrically conductive floating gate having a first portion disposed vertically over and insulated from a first portion of the channel region, and a second portion disposed vertically over and insulated from the first region, wherein the floating gate includes a sloping upper surface that terminates with one or more sharp edges;

an electrically conductive erase gate disposed vertically over and insulated from the floating gate, wherein the one or more sharp edges face and are insulated from the erase gate;

an electrically conductive control gate having a first portion disposed laterally adjacent to and insulated from the floating gate, and vertically over and insulated from the first region; and

an electrically conductive select gate having a first portion disposed vertically over and insulated from a second portion of the channel region, and laterally adjacent to and insulated from the floating gate.

2. The non-volatile memory cell of claim 1, wherein the control gate has a second portion disposed laterally adjacent to and insulated from the erase gate.

3. The non-volatile memory cell of claim 1, wherein the select gate has a second portion disposed laterally adjacent to and insulated from the erase gate.

4. The non-volatile memory cell of claim 1, wherein the select gate is a spacer.

5. The non-volatile memory cell of claim 1, wherein the floating gate includes:

a bottom surface facing the first portion of the channel region and the first region; and

a side surface facing the control gate;

wherein the side surface has a vertical length that is greater than a horizontal length of the bottom surface.

6. The non-volatile memory cell of claim 1, wherein the one or more sharp edges are a pair of sharp edges at opposing sides of the upper surface of the floating gate.

7. An array of non-volatile memory cells, comprising:

a substrate of semiconductor material of a first conductivity type;

spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;

each of the active regions including pairs of memory cells, each of the memory cell pairs including;

a first region and a pair of second regions spaced apart in the substrate having a second conductivity type different from the first conductivity type, with channel regions in the substrate between the first region and the second regions,

a pair of electrically conductive floating gates each having a first portion disposed vertically over and insulated from a first portion of one of the channel regions, and a second portion disposed vertically over and insulated from the first region, wherein each of the floating gates includes a sloping upper surface that terminates with one or more sharp edges,

a pair of electrically conductive erase gates each one disposed vertically over and insulated from one of the floating gates wherein the one or more sharp edges of the one floating gate face the one erase gate,

an electrically conductive control gate having a first portion disposed laterally adjacent to and insulated from the floating gates, and vertically over and insulated from the first region, and

a pair of electrically conductive select gates each having a first portion disposed vertically over and insulated from a second portion of one of the channel regions, and laterally adjacent to and insulated from one of the floating gates.

8. The array of claim 7, wherein for each of the memory cell pairs, the control gate has a second portion disposed laterally between and insulated from the pair of erase gates.

9. The array of claim 7, wherein each of the select gates has a second portion disposed laterally adjacent to and insulated from one of the erase gates.

10. The array of claim 7, wherein each of the select gates is a spacer.

11. The array of claim 7, wherein for each of the memory cell pairs, each of the floating gates includes:

a bottom surface facing the first portion of one of the channel regions and the first region; and

a side surface facing the control gate;

wherein the side surface has a vertical length that is greater than a horizontal length of the bottom surface.

12. The array of claim 7, wherein each of the erase gates is formed as part of a conductive erase gate line that extends across the active regions and the isolation regions in a second direction perpendicular to the first direction, and wherein each of the erase gate lines intercepts one of the erase gates in each of the active regions.

13. The array of claim 12, wherein for each of the floating gates, the one or more sharp edges are a pair of sharp edges at opposing sides of the upper surface of the floating gate, and wherein each of the erase gate lines extends over the pair of sharp edges of one of the floating gates in each of the active regions.

14. A method of forming a non-volatile memory cell, comprising:

providing a substrate of semiconductor material of a first conductivity type;

forming first and second spaced-apart regions in the substrate of a second conductivity type different from the first conductivity type, with a channel region in the substrate therebetween;

forming an electrically conductive floating gate having a first portion disposed vertically over and insulated from a first portion of the channel region, and a second portion disposed vertically over and insulated from the first region, wherein the floating gate includes a sloping upper surface that terminates with one or more sharp edges;

forming an electrically conductive erase gate disposed vertically over and insulated from the floating gate, wherein the one or more sharp edges face and are insulated from the erase gate;

forming an electrically conductive control gate having a first portion disposed laterally adjacent to and insulated from the floating gate, and vertically over and insulated from the first region; and

forming an electrically conductive select gate having a first portion disposed vertically over and insulated from a second portion of the channel region, and laterally adjacent to and insulated from the floating gate.

15. The method of claim 14, wherein the forming of the select gate includes forming a spacer of conductive material.

16. The method of claim 14, wherein the floating gate includes:

a bottom surface facing the first portion of the channel region and the first region; and

a side surface facing the control gate;

wherein the side surface has a vertical length that is greater than a horizontal length of the bottom surface.

17. The method of claim 14, wherein the one or more sharp edges are a pair of sharp edges at opposing sides of the upper surface of the floating gate.

18. A method of forming an array of non-volatile memory cells, comprising:

providing a substrate of semiconductor material of a first conductivity type;

forming spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;

forming pairs of memory cells in each of the active regions, each of the pairs of memory cells is formed by;

forming a first region and a pair of second regions spaced apart in the substrate having a second conductivity type different from the first conductivity type, with channel regions in the substrate between the first region and the second regions,

forming a pair of electrically conductive floating gates each having a first portion disposed vertically over and insulated from a first portion of one of the channel regions, and a second portion disposed vertically over and insulated from the first region, wherein each of the floating gates includes a sloping upper surface that terminates with one or more sharp edges,

forming a pair of electrically conductive erase gates each one disposed vertically over and insulated from one of the floating gates wherein the one or more sharp edges of the one floating gate face the one erase gate,

forming an electrically conductive control gate having a first portion disposed laterally adjacent to and insulated from the floating gates, and vertically over and insulated from the first region, and

forming a pair of electrically conductive select gates each having a first portion disposed vertically over and insulated from a second portion of one of the channel regions, and laterally adjacent to and insulated from one of the floating gates.

19. The method of claim 18, wherein the forming of each of the select gates includes forming a spacer of conductive material.

20. The method of claim 18, wherein for each of the memory cell pairs, each of the floating gates includes:

a bottom surface facing the first portion of one of the channel regions and the first region, and

a side surface facing the control gate,

wherein the side surface has a vertical length that is greater than a horizontal length of the bottom surface.

21. The method of claim 18, wherein each of the erase gates is formed as part of a conductive erase gate line that extends across the active regions and the isolation regions in a second direction perpendicular to the first direction, and wherein each of the erase gate lines intercepts one of the erase gates in each of the active regions.

22. The method of claim 21, wherein for each of the floating gates, the one or more sharp edges are a pair of sharp edges at opposing sides of the upper surface of the floating gate, and wherein each of the erase gate lines extends over the pair of sharp edges of one of the floating gates in each of the active regions.