SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

• US 20160043186A1
• Filed: 08/08/2014
• Published: 02/11/2016
• Est. Priority Date: 08/08/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: TSAI, Chia-Ming, LIN, Shih-Chi, LIU, Ke-Chih
• Granted Patent: US 9,601,593 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76855 After-treatment introducing at least one additional element into the layer
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a gate stack positioned over the semiconductor substrate. The gate stack includes a gate dielectric layer and a gate electrode over the gate dielectric layer. The semiconductor device structure includes spacers positioned over first sidewalls of the gate stack. The spacers and the gate stack surround a recess. The semiconductor device structure includes an insulating layer formed over the semiconductor substrate and surrounding the gate stack. The semiconductor device structure includes a cap layer covering the insulating layer, the spacers, and inner walls of the recess.

Claims

1. A semiconductor device structure, comprising:

a semiconductor substrate;

a gate stack positioned over the semiconductor substrate, wherein the gate stack comprises a gate dielectric layer and a gate electrode over the gate dielectric layer;

spacers positioned over first sidewalls of the gate stack, wherein the spacers and the gate stack surround a recess;

an insulating layer formed over the semiconductor substrate and surrounding the gate stack; and

a cap layer covering the insulating layer, the spacers, and inner walls of the recess, wherein the cap layer is located above a top of the insulating layer.

2. The semiconductor device structure as claimed in claim 1, wherein the gate stack further comprises a work function layer positioned between the gate electrode and the gate dielectric layer and between the gate electrode and the spacers, and the recess is positioned over the work function layer.

3. The semiconductor device structure as claimed in claim 1, wherein the cap layer comprises oxide or nitride.

4. The semiconductor device structure as claimed in claim 1, wherein the cap layer conformally covers the inner walls and a bottom surface of the recess.

5. The semiconductor device structure as claimed in claim 1, further comprising:

an etch stop layer positioned over the cap layer.

6. The semiconductor device structure as claimed in claim 1, wherein the cap layer has a first layer and a second layer over the first layer.

7. The semiconductor device structure as claimed in claim 6, wherein the first layer conformally covers the insulating layer and the inner walls and a bottom surface of the recess.

8. The semiconductor device structure as claimed in claim 1, wherein the semiconductor substrate has a source region and a drain region positioned at two opposite sides of the gate stack, respectively, and the semiconductor device structure further comprises:

contact plugs penetrating through the cap layer and the insulating layer to electrically connect to the source region and the drain region, respectively.

21. The semiconductor device structure as claimed in claim 1, wherein the recess has a depth, the gate electrode has a thickness, and a ratio of the depth to the thickness ranges from about 0.05 to about 0.25.

22. The semiconductor device structure as claimed in claim 1, wherein the gate stack further comprises a work function layer positioned between the gate electrode and the gate dielectric layer and between the gate electrode and the spacers, such that the recess is positioned in the work function layer.

23. The semiconductor device structure as claimed in claim 8, wherein the semiconductor device structure further comprises:

stressors formed in the source region and the drain region, respectively.

9. A semiconductor device structure, comprising:

a semiconductor substrate;

a gate stack formed over the semiconductor substrate, wherein the gate stack comprises a gate dielectric layer and a gate electrode over the gate dielectric layer;

spacers positioned over sidewalls of the gate stack, wherein the spacers and the gate stack surround a recess;

an insulating layer formed over the semiconductor substrate and surrounding the gate stack; and

a cap layer positioned over a top of the insulating layer and extending into the recess to fill the recess.

10. The semiconductor device structure as claimed in claim 9, wherein the cap layer in the recess is in direct contact with the spacers.

11. The semiconductor device structure as claimed in claim 9, wherein the cap layer comprises oxide or nitride.

12. The semiconductor device structure as claimed in claim 9, wherein the cap layer has a first layer and a second layer over the first layer, and a first thickness of the first layer is less than a second thickness of the second layer.

13. The semiconductor device structure as claimed in claim 12, wherein the first layer comprises metal oxide, and the second layer comprises nitride.

14. The semiconductor device structure as claimed in claim 9, wherein the recess has a depth, the gate electrode has a thickness, and a ratio of the depth to the thickness ranges from about 0.05 to about 0.25.

15. The semiconductor device structure as claimed in claim 9, wherein the semiconductor substrate has a source region and a drain region positioned at two opposite sides of the gate stack, respectively, and the semiconductor device structure further comprises:

contact plugs penetrating through the cap layer and the insulating layer to electrically connect to the source region and the drain region, respectively, and first top surfaces of the contact plugs are aligned with a second top surface of the cap layer.

24. The semiconductor device structure as claimed in claim 9, wherein the gate stack further comprises a work function layer positioned between the gate electrode and the gate dielectric layer and between the gate electrode and the spacers, such that the cap layer in the recess is separated from the spacers by the work function layer.

25. The semiconductor device structure as claimed in claim 15, wherein the semiconductor device structure further comprises:

stressors formed in the source region and the drain region, respectively.

16-20. -20. (canceled)