Selective Polysilicon Doping for Gate Induced Drain Leakage Improvement

• US 20160043188A1
• Filed: 08/06/2014
• Published: 02/11/2016
• Est. Priority Date: 08/06/2014
• Status: Active Application

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chu, Chen-Liang, Yao, Chih-Wen, Liu, Ruey-Hsin, Lei, Ming-Ta
• Granted Patent: US 10,276,596 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28105 the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

Some embodiments of the present disclosure relate to deceasing off-state leakage current within a metal-oxide-semiconductor field-effect transistor (MOSFET). The MOSFET includes source and drain regions. The source and drain regions are separated by a channel region. A gate is arranged over the channel region. The gate has a first gate region adjacent to the source region and a second gate region adjacent to the drain region. The first gate region is selectively doped adjacent the source region. The second gate region is undoped or lightly-doped. The undoped or lightly-doped second gate region reduces the electric field between the gate and the drain region, and hence reduces a gate induced drain leakage (GIDL) current between the gate and drain region. The undoped or lightly-doped region of the gate can reduce the GIDL current within the MOSFET by about three orders of magnitude. Other embodiments are also disclosed.

Claims

1. A transistor, comprising:

a source region and a drain region, which are separated by a channel region; and

a gate separated from the channel region by a gate dielectric, the gate comprising;

a first gate region having a first dopant concentration, which is adjacent the source region; and

a second gate region having a second dopant concentration, which is adjacent the drain region, wherein the second dopant concentration is less than the first dopant concentration.

2. The transistor of claim 1,

wherein a first length of the first gate region is greater than a second length of the second gate region;

and

wherein the first and second lengths are measured along a channel length direction of the transistor.

3. The transistor of claim 1, wherein the second dopant is at least an order of magnitude less than the first dopant concentration.

4. The transistor of claim 1, further comprising a silicide layer arranged on the first gate region.

5. The transistor of claim 4, wherein a portion of the first gate region extends laterally past the silicide layer.

6. The transistor of claim 1,

wherein the gate comprises polysilicon;

and

wherein the first gate region comprises nitrogen (N), phosphorous (P), arsenic (As), antimony (Sb), or bismuth (Bi).

7. The transistor of claim 1, wherein the source region or drain region comprises:

a deeper doped region having a first conductivity type and a third dopant concentration; and

a shallow doped region arranged within the deeper doped region, and comprising the first conductivity type and a fourth dopant concentration, which is greater than the third dopant concentration;

wherein the channel region comprises a second conductivity type, which is different than the first conductivity type.

8. The transistor of claim 7,

wherein the deeper doped region of the source region extends beneath the first gate region;

and

wherein the deeper doped region of the drain region extends beneath the second gate region.

9. A circuit comprising:

a first transistor, comprising;

a first source region and a first drain region each having a first conductivity type, which are disposed within a semiconductor substrate having a second conductivity type between the first source region and the first drain region;

a first gate arranged over the semiconductor substrate at a position laterally between the first source region and the first drain region, the first gate comprising;

a doped gate region abutting a first sidewall of the gate adjacent the first source region; and

an undoped gate region abutting a second sidewall of the gate adjacent the first drain region, which opposes the first sidewall.

10. The circuit of claim 9, further comprising:

a second transistor arranged in parallel with the first transistor;

wherein the first source of the first transistor and a second source of the second transistor are connected to ground through a first common node;

wherein the first drain of the first transistor and a second drain of the second transistor are connected to a power source; and

wherein the first gate of the first transistor and a second gate of the second transistor are connected to a differential input comprising first and second input voltages.

11. The circuit of claim 10,

wherein the first and second drains are respectively connected to the power source through first and second access transistors;

wherein gates of the first and second access transistors are connected to a source of the first access transistor through a second common node; and

wherein a source of the second access transistor is connected to an output of the circuit.

12. The circuit of claim 10, wherein the first and second sources are connected to ground through a third access transistor.

13. The circuit of claim 9, further comprising a silicide layer comprising the first conductivity type arranged on the doped gate region, wherein a portion of the doped gate region extends laterally past the silicide layer.

14. The circuit of claim 9, wherein the doped gate region comprises nitrogen (N), phosphorous (P), arsenic (As), antimony (Sb), or bismuth (Bi).

15. The circuit of claim 9,

wherein the source region extends beneath the doped gate region;

and

wherein the drain region extends beneath the undoped gate region.

16. A method of forming a transistor, comprising:

forming a source region and a drain region within a semiconductor substrate;

forming a gate dielectric over a channel region of the semiconductor substrate, at a position laterally arranged between the source region and the drain region;

forming a gate over the gate dielectric; and

selectively doping a first region of the gate adjacent the source region, while leaving a second region of the gate adjacent to the drain region undoped.

17. The method of claim 16, wherein selectively doping the first region of the gate comprises:

forming a mask over the semiconductor substrate, wherein the mask has an opening over the first region of the gate; and

implanting the gate with dopants through the opening.

18. The method of claim 17, wherein the dopants comprise nitrogen (N), phosphorous (P), arsenic (As), antimony (Sb), or bismuth (Bi).

19. The method of claim 16, further comprising forming a silicide layer on the first region of the gate, wherein a portion of the first region of the gate adjacent the second region of the gate extends laterally past the silicide layer.

20. The method of claim 16, wherein forming the source region or the drain region comprises:

forming a deeper doped region having a first conductivity type and a first dopant concentration; and

forming a shallow doped region within the deeper doped region, and comprising the first conductivity type and a second dopant concentration, which is greater than the first dopant concentration;

wherein the semiconductor substrate comprises a second conductivity type, which is different than the first conductivity type.