SHARING FIRMWARE AMONG AGENTS IN A COMPUTING NODE

• US 20160048184A1
• Filed: 03/29/2013
• Published: 02/18/2016
• Est. Priority Date: 03/29/2013
• Status: Abandoned Application

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Basile, Barry S, Brown, Andrew, Stearns, Michael, Hua, Chanh V, Hansen, Peter, Francom, Jared K, Cepulis, Darren J
• Application Number:
  US14/781,299
• Publication Number:
  US 20160048184A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/266 Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
• CPC Class Codes: G06F 13/20 for access to input/output bus
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 8/65 Updates security arrangements therefor G06F21/57
• CPC Class Codes: G06F 8/654 using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
• CPC Class Codes: G06F 9/4405 Initialisation of multiprocessor systems
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Sharing firmware among a plurality of agents including a plurality of central processing units (CPUs) on a node is described. In an example, a computing node includes: a bus; a non-volatile memory, coupled to the bus, to store firmware for the plurality of agents; a power sequencer to implement a power-up sequence for the plurality of CPUs; a plurality of power control state machines respectively controlling states of the plurality of CPUs based on output of the power sequencer; and a bus controller to selectively couple the plurality of agents to the non-volatile memory based on state of the plurality of power control state machines.

Claims

1. An apparatus to share firmware among a plurality of agents including a plurality of central processing units (CPUs) on a node, comprising:

a bus;

a non-volatile memory, coupled to the bus, to store firmware for the plurality of agents;

a power sequencer to implement a power-up sequence for the plurality of CPUs;

a plurality of power control state machines respectively controlling states of the plurality of CPUs based on output of the power sequencer;

a bus controller to selectively couple the plurality of agents to the non-volatile memory based on state of the plurality of power control state machines.

2. The apparatus of claim 1, wherein the bus controller includes:

a bus arbiter to select one of the plurality of agents for communication with the non-volatile memory; and

a bus multiplexer to establish a communication link between the non-volatile memory and the one of the plurality of agents as selected by the bus arbiter.

3. The apparatus of claim 1, wherein the bus is a serial data bus.

4. The apparatus of claim 1, wherein the plurality of agents further includes a management agent to load images of the firmware to the non-volatile memory.

5. The apparatus of claim 1, wherein each of the plurality of power control state machines hold a respective one of the plurality of CPUs in reset until selected by the power sequencer for power-up.

6. A method of sharing firmware among a plurality of agents including a plurality of central processing units (CPUs) connected to a bus on a node, comprising:

storing firmware for the plurality of agents in a non-volatile memory coupled to the bus;

implementing a power-up sequence for the plurality of CPUs;

controlling states of the plurality of CPUs based on the power-up sequence; and

selectively coupling the plurality of agents to the non-volatile memory based on the states of the plurality of CPUs.

7. The method of claim 6, wherein the step of controlling the states comprises:

selecting a CPU of the plurality of CPUs permitted to power-up based on the power-up sequence;

granting the CPU access to the non-volatile memory;

maintain each of the plurality of CPUs other than the selected CPU in a reset state; and

repeating the steps of selecting, granting, and maintaining for at least one additional CPU of the plurality of CPUs.

8. The method of claim 6, further comprising:

granting a management process access to the non-volatile memory to update the firmware stored therein.

9. The method of claim 6, further comprising:

receiving requests for access to the non-volatile memory from requesting agents of the plurality of agents; and

successively granting exclusive access to the requesting agents based on the requests.

10. The method of claim 6, wherein the bus is a serial data bus.

11. A computer system, comprising:

at least one node, including;

a plurality of agents including a plurality of central processing units (CPUs);

a bus;

a non-volatile memory coupled to the bus, to store firmware for the plurality of agents; and

an integrated circuit, coupled to the bus, including;

a power sequencer to implement a power-up sequence for the plurality of CPUs;

a plurality of power control state machine respectively controlling states of the plurality of CPUs based on output of the power sequencer circuit;

a bus controller to selectively couple the plurality of agents to the non-volatile memory based on state of the plurality of power control state machine circuits.

12. The computer system of claim 11, wherein the bus controller includes:

a bus arbiter to select one of the plurality of agents for communication with the non-volatile memory; and

a bus multiplexer to establish a communication link between the non-volatile memory and the one of the plurality of agents as selected by the bus arbiter.

13. The computer system of claim 11, wherein the bus is a serial data bus.

14. The computer system of claim 11, wherein the plurality of agents further includes a management agent to load images of the firmware to the non-volatile memory.

15. The computer system of claim 11, wherein each of the plurality of power control state machine hold a respective one of the plurality of CPUs in reset until selected by the power sequencer for power-up.