CIRCUIT AND LAYOUT DESIGN METHODS AND LOGIC CELLS FOR SOFT ERROR HARD INTEGRATED CIRCUITS

• US 20160048624A1
• Filed: 03/23/2015
• Published: 02/18/2016
• Est. Priority Date: 01/17/2008
• Status: Abandoned Application

• Current Assignee: Klas Olof Lilja
• Original Assignee: Klas Olof Lilja
• Inventors: Lilja, Klas Olof
• Application Number:
  US14/666,043
• Publication Number:
  US 20160048624A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H03K 19/0033 Radiation hardening
• CPC Class Codes: H03K 19/00338 In field effect transistor circuits
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

In various embodiments, an integrated circuit derived from an integrated circuit layout is disclosed. In some embodiments, the integrated circuit layout comprises a first contact area from a first logic cell and a second contact area from a second logic cell. The second contact area comprises a non-zero, non-opposing effect with respect to the first contact area. The first contact area and the second contact area comprise a first distance. When the first distance is below a predetermined threshold, the first logic cell and the second logic cell are placed along a first R-line of the circuit and a third contact area comprising an opposing effect with respect to the first contact area and the second contact area is placed between the first contact area and second contact area.

Claims

1. An integrated circuit comprising logic cells with one or more sets of two complementary inputs and one or more sets of two complementary outputs, the integrated circuit derived from an integrated circuit layout comprising:

a first contact area from a first logic cell;

a second contact area from a second logic cell comprising a non-zero, non-opposing effect with respect to the first contact area, wherein the first contact area and the second contact area comprise a first distance, and

wherein;

when the first distance is below a predetermined threshold, the first logic cell and the second logic cell are placed along a first R-line of the integrated circuit such that a third contact area, from either of the first or second logic cells, comprising an opposing effect with respect to the first contact area and the second contact area, is placed between the first contact area and second contact area; and

when the first distance is not below the predetermined threshold;

a filter cell is inserted between the first contact area and the second contact area, the filter cell configured to decouple the first logic cell and the second logic cells; and

the first contact area is placed along the first R-line and the second contact area is placed along a second R-line of the integrated circuit.

2. The integrated circuit of claim 1, wherein the filter cell is placed at least partially along the second R-line when the first distance is not below the predetermined threshold.

3. The integrated circuit of claim 2, wherein the filter cell comprises a first circuit path comprising one or more contact areas placed along the first R-line and a second circuit path placed along the second R-line.

4. The integrated circuit of claim 1, wherein the filter cell comprises:

a first p-type MOSFET comprising a first source coupled to a power net, a first drain, and a first gate coupled to an input;

a second p-type MOSFET comprising a second source coupled to the first drain of the first p-type MOSFET, a second drain coupled to an inverse output, and a second gate coupled to an inverse of a complementary signal of the input;

a third p-type MOSFET comprising a third source coupled to the power net, a third drain, and a third gate coupled to the complementary signal of the input;

a fourth p-type MOSFET comprising a fourth source coupled to the third drain of the third p-type MOSFET, a fourth drain coupled to an output, and a fourth gate coupled to an inverse of the input;

a first n-type MOSFET comprising a fifth source coupled to a ground net, a fifth drain, and a fifth gate coupled to the input;

a second n-type MOSFET comprising a sixth source coupled to the fifth drain of the first n-type MOSFET, a sixth drain coupled to the inverse output, and a sixth gate coupled to the inverse of the complementary signal of the input;

a third n-type MOSFET comprising a seventh source coupled to the ground net, a seventh drain, and a seventh gate coupled to the complementary signal of the first input; and

a fourth n-type MOSFET comprising an eighth source coupled to the seventh drain of the third n-type MOSFET, an eighth drain coupled to the output, and an eighth gate coupled to the inverse of the input.

5. A method of designing an integrated circuit comprising logic cells with one or more sets of two complementary inputs and one or more sets of two complementary outputs, the integrated circuit derived from an integrated circuit layout, the method comprising:

accessing in the integrated circuit layout, by a processor, a first contact area from a first logic cell;

accessing in the integrated circuit layout, by the processor, a second contact area from a second logic cell comprising a non-zero, non-opposing effect with respect to the first contact area;

determining, by the processor, a first distance between the first contact area and the second contact area;

determining, by the processor, whether the first distance is below a predetermined threshold;

when it is determined the first distance is below the predetermined threshold;

placing in the integrated circuit layout, by the processor, the first logic cell and the second logic cell along a first R-line of the integrated circuit; and

placing in the integrated circuit layout, by the processor, a third contact area, from either of the first or second logic cells, comprising an opposing effect with respect to the first contact area and the second contact area, such that the third contact area is placed between the first contact area and second contact area; and

when it is determined that the first distance is not below the predetermined threshold;

inserting in the integrated circuit layout, by the processor, a filter cell between the first contact area and the second contact area, the filter cell configured to decouple the first logic cell and the second logic cells;

placing in the integrated circuit layout, by the processor, the first contact area along the first R-line; and

placing in the integrated circuit layout, by the processor, the second contact area along a second R-line of the integrated circuit.

6. The method of claim 5, further comprising placing the filter cell at least partially along the second R-line when it is determined the first distance is not below the predetermined threshold.

7. The method of claim 6, wherein the filter cell comprises a first circuit path comprising one or more contact areas placed along the first R-line and a second circuit path placed along the second R-line.

8. The method of claim 5, wherein the filter cell comprises:

a first p-type MOSFET comprising a first source coupled to a power net, a first drain, and a first gate coupled to an input;

a second p-type MOSFET comprising a second source coupled to the first drain of the first p-type MOSFET, a second drain coupled to an inverse output, and a second gate coupled to an inverse of a complementary signal of the input;

a third p-type MOSFET comprising a third source coupled to the power net, a third drain, and a third gate coupled to the complementary signal of the input;

a fourth p-type MOSFET comprising a fourth source coupled to the third drain of the third p-type MOSFET, a fourth drain coupled to an output, and a fourth gate coupled to an inverse of the input;

a first n-type MOSFET comprising a fifth source coupled to a ground net, a fifth drain, and a fifth gate coupled to the input;

a second n-type MOSFET comprising a sixth source coupled to the fifth drain of the first n-type MOSFET, a sixth drain coupled to the inverse output, and a sixth gate coupled to the inverse of the complementary signal of the input;

a third n-type MOSFET comprising a seventh source coupled to the ground net, a seventh drain, and a seventh gate coupled to the complementary signal of the first input; and

a fourth n-type MOSFET comprising an eighth source coupled to the seventh drain of the third n-type MOSFET, an eighth drain coupled to the output, and an eighth gate coupled to the inverse of the input.

9. A non-transitory computer readable medium comprising instructions that, when executed by a processor, cause a machine to perform operations comprising:

accessing in an integrated circuit layout a first contact area from a first logic cell;

accessing in the integrated circuit layout a second contact area from a second logic cell comprising a non-zero, non-opposing effect with respect to the first contact area;

determining a first distance between the first contact area and the second contact area;

determining whether the first distance is below a predetermined threshold;

when it is determined the first distance is below the predetermined threshold;

placing in the integrated circuit layout the first logic cell and the second logic cell along a first R-line of the integrated circuit; and

placing in the integrated circuit layout a third contact area, from either of the first or second logic cells, comprising an opposing effect with respect to the first contact area and the second contact area, such that the third contact area is placed between the first contact area and second contact area; and

when it is determined that the first distance is not below the predetermined threshold;

inserting in the integrated circuit layou a filter cell between the first contact area and the second contact area, the filter cell configured to decouple the first logic cell and the second logic cells;

placing in the integrated circuit layout the first contact area along the first R-line; and

placing in the integrated circuit layout the second contact area along a second R-line of the integrated circuit.

10. The computer readable medium of claim 9, wherein the operations further comprise placing the filter cell at least partially along the second R-line when it is determined the first distance is not below the predetermined threshold.

11. The computer readable medium of claim 10, wherein the filter cell comprises a first circuit path comprising one or more contact areas placed along the first R-line and a second circuit path placed along the second R-line.

12. The computer readable medium of claim 9, wherein the filter cell comprises:

a first p-type MOSFET comprising a first source coupled to a power net, a first drain, and a first gate coupled to an input;

a second p-type MOSFET comprising a second source coupled to the first drain of the first p-type MOSFET, a second drain coupled to an inverse output, and a second gate coupled to an inverse of a complementary signal of the input;

a third p-type MOSFET comprising a third source coupled to the power net, a third drain, and a third gate coupled to the complementary signal of the input;

a fourth p-type MOSFET comprising a fourth source coupled to the third drain of the third p-type MOSFET, a fourth drain coupled to an output, and a fourth gate coupled to an inverse of the input;

a first n-type MOSFET comprising a fifth source coupled to a ground net, a fifth drain, and a fifth gate coupled to the input;

a second n-type MOSFET comprising a sixth source coupled to the fifth drain of the first n-type MOSFET, a sixth drain coupled to the inverse output, and a sixth gate coupled to the inverse of the complementary signal of the input;

a third n-type MOSFET comprising a seventh source coupled to the ground net, a seventh drain, and a seventh gate coupled to the complementary signal of the first input; and

a fourth n-type MOSFET comprising an eighth source coupled to the seventh drain of the third n-type MOSFET, an eighth drain coupled to the output, and an eighth gate coupled to the inverse of the input.