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CIRCUIT AND LAYOUT DESIGN METHODS AND LOGIC CELLS FOR SOFT ERROR HARD INTEGRATED CIRCUITS

  • US 20160048624A1
  • Filed: 03/23/2015
  • Published: 02/18/2016
  • Est. Priority Date: 01/17/2008
  • Status: Abandoned Application
First Claim
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1. An integrated circuit comprising logic cells with one or more sets of two complementary inputs and one or more sets of two complementary outputs, the integrated circuit derived from an integrated circuit layout comprising:

  • a first contact area from a first logic cell;

    a second contact area from a second logic cell comprising a non-zero, non-opposing effect with respect to the first contact area, wherein the first contact area and the second contact area comprise a first distance, andwherein;

    when the first distance is below a predetermined threshold, the first logic cell and the second logic cell are placed along a first R-line of the integrated circuit such that a third contact area, from either of the first or second logic cells, comprising an opposing effect with respect to the first contact area and the second contact area, is placed between the first contact area and second contact area; and

    when the first distance is not below the predetermined threshold;

    a filter cell is inserted between the first contact area and the second contact area, the filter cell configured to decouple the first logic cell and the second logic cells; and

    the first contact area is placed along the first R-line and the second contact area is placed along a second R-line of the integrated circuit.

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