STROBE GATING ADAPTION AND TRAINING IN A MEMORY CONTROLLER

• US 20160049183A1
• Filed: 08/12/2015
• Published: 02/18/2016
• Est. Priority Date: 08/15/2014
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Mishra, Navin Kumar, Mahabaleshwara, Mahabaleshwara, Bose, Soumya, Puzhankara, Abhilash, Swamiappan, Karthikeyan
• Granted Patent: US 9,514,420 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06N 20/00 Machine learning
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/067 Single-ended amplifiers
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

A memory controller includes a differential receiver circuitry to receive a differential data strobe signal pair and to generate a first data strobe signal based on the differential data strobe signal pair. The differential data strobe signal pair comprises a first signal and a second signal. The memory controller also includes a single ended receiver circuitry to receive the first signal of the differential data strobe signal pair and to generate a second data strobe signal based on the first signal of the differential data strobe signal pair. The memory controller further includes circuitry to generate a gating signal for gating the first data strobe signal, the circuitry generating the gating signal based on the second data strobe signal.

Claims

1. A memory controller comprising:

differential receiver circuitry to receive a differential data strobe signal pair and to generate a first data strobe signal based on the differential data strobe signal pair, the differential data strobe signal pair comprised of a first signal and a second signal;

single ended receiver circuitry to receive the first signal of the differential data strobe signal pair and to generate a second data strobe signal based on the first signal of the differential data strobe signal pair; and

circuitry to generate a gating signal for gating the first data strobe signal, the circuitry generating the gating signal based on the second data strobe signal.

2. The memory controller of claim 1, wherein the gating signal is indicative of an active data strobe window, and the circuitry triggers a start of the active data strobe window based on the second data strobe signal.

3. The memory controller of claim 1, wherein the circuitry generates the gating signal further based on the first data strobe signal.

4. The memory controller of claim 1, wherein the circuitry receives a gate strobe signal indicative of an active data strobe window and generates the gating signal further based on the gate strobe signal, the gating signal indicative of an adjusted version of the active data strobe window.

5. The memory controller of claim 4, further comprising:

training circuitry to calibrate the active data strobe window of the gate strobe signal based on the second data strobe signal.

6. The memory controller of claim 5, wherein the training circuitry comprises:

a first sampling circuit to generate a first data strobe sample by sampling the second data strobe signal at a rising edge of the gate strobe signal; and

a second sampling circuit to generate a second data strobe sample by sampling the second data strobe signal at a falling edge of the gate strobe signal;

wherein the training circuitry calibrates the active data strobe window based on the first data strobe sample and the second data strobe sample.

7. The memory controller of claim 1, wherein the differential receiver circuitry comprises a comparator to compare the first and second signals of the differential data strobe signal pair and to generate the first data strobe signal based on the comparison.

8. The memory controller of claim 1, wherein the single ended receiver circuitry comprises a comparator to compare the first signal from the differential data strobe signal pair to a reference voltage signal, and to generate the second data strobe signal based on the comparison.

9. A method of operation in a memory controller, the method comprising:

receiving, at a differential receiver, a differential data strobe signal pair, the differential data strobe signal pair comprised of a first signal and a second signal;

generating, by the differential receiver, a first data strobe signal based on the differential data strobe signal pair;

receiving, at a single ended receiver, the first signal of the differential data strobe signal pair;

generating, by the single ended receiver, a second data strobe signal based on the first signal of the differential data strobe signal pair; and

generating a gating signal for gating the first data strobe signal, the gating signal generated based on the second data strobe signal.

10. The method of claim 9, wherein the gating signal is indicative of an active data strobe window;

and the method further comprises

triggering a start of the active data strobe window based on the second data strobe signal.

11. The method of claim 9, wherein the generating of the gating signal is further based on the first data strobe signal.

12. The method of claim 9, further comprising:

receiving a gate strobe signal indicative of an active data strobe window; and

generating the gating signal further based on the gate strobe signal, the gating signal indicative of an adjusted version of the active data strobe window.

13. The method of claim 12, further comprising calibrating the active data strobe window of the gate strobe signal based on the second data strobe signal.

14. The method of claim 12, further comprising:

generating a first data strobe sample by sampling the second data strobe signal at a rising edge of the gate strobe signal;

generating a second data strobe sample by sampling the second data strobe signal at a falling edge of the gate strobe signal; and

calibrating the active data strobe window based on the first data strobe sample and the second data strobe sample.

15. The method of claim 9, wherein generating the first data strobe signal comprises:

comparing the first and second signals of the differential data strobe signal pair; and

generating the first data strobe signal based on the comparison.

16. The method of claim 9, wherein generating the second data strobe signal comprises:

comparing the first signal from the differential data strobe signal pair and a reference voltage signal; and

generating the second data strobe signal based on the comparison.

17. A non-transitory computer readable medium storing a representation of a memory controller, the memory controller comprising:

differential receiver circuitry to receive a differential data strobe signal pair and to generate a first data strobe signal based on the differential data strobe signal pair, the differential data strobe signal pair comprised of a first signal and a second signal;

single ended receiver circuitry to receive the first signal of the differential data strobe signal pair and to generate a second data strobe signal based on the first signal of the differential data strobe signal pair; and

circuitry to generate a gating signal for gating the first data strobe signal, the circuitry generating the gating signal based on the second data strobe signal.

18. The computer readable medium of claim 17, wherein the circuitry receives a gate strobe signal indicative of an active data strobe window and generates the gating signal further based on the gate strobe signal, the gating signal indicative of an adjusted version of the active data strobe window.

19. The computer readable medium of claim 18, the controller further comprising:

training circuitry to calibrate the active data strobe window of the gate strobe signal based on the second data strobe signal.

20. The computer readable medium of claim 19, wherein the training circuitry comprises:

a first sampling circuit to generate a first data strobe sample by sampling the second data strobe signal at a rising edge of the gate strobe signal; and

a second sampling circuit to generate a second data strobe sample by sampling the second data strobe signal at a falling edge of the gate strobe signal;

wherein the training circuitry calibrates the active data strobe window based on the first data strobe sample and the second data strobe sample.