BUFFER LAYER(S) ON A STACKED STRUCTURE HAVING A VIA

• US 20160049384A1
• Filed: 08/13/2014
• Published: 02/18/2016
• Est. Priority Date: 08/13/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lu, Chen-Fa, Tsai, Cheng-Yuan, Tu, Yeur-Luen, Tsai, Chia-Shiung
• Granted Patent: US 9,793,243 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/02125 Reinforcing structures
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/02351 comprising interlocking features
• CPC Class Codes: H01L 2224/024 Material of the insulating layers therebetween
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/0558 being stacked
• CPC Class Codes: H01L 2224/05644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/08145 : the bodies being stacked
• CPC Class Codes: H01L 2224/08146 : the bonding area connecting to a via connection in the body
• CPC Class Codes: H01L 2224/11 : Manufacturing methods
• CPC Class Codes: H01L 2224/1132 : Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/1145 : Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/11462 : Electroplating
• CPC Class Codes: H01L 2224/11849 : Reflowing
• CPC Class Codes: H01L 2224/12105 : Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13024 : the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/80001 : by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/8034 : Bonding interfaces of the bonding area
• CPC Class Codes: H01L 2224/80895 : between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 : between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/80986 : Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
• CPC Class Codes: H01L 2224/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/8203 : Reshaping, e.g. forming vias
• CPC Class Codes: H01L 2224/821 : Forming a build-up interconnect
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/9212 : Sequential connecting processes
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 23/293 : Organic, e.g. plastic
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/09 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/89 : using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/014 : Solder alloys

Abstract

A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.

Claims

1-14. -14. (canceled)

15. A method comprising:

bonding a first substrate to a second substrate, the second substrate comprising a semiconductor substrate;

forming a via from a side of the semiconductor substrate and at least extending through the semiconductor substrate;

forming a first stress buffer layer on the side of the semiconductor substrate;

forming a post-passivation interconnect (PPI) structure on the first stress buffer layer and electrically coupled to the via; and

forming a second stress buffer layer on the PPI structure and the first stress buffer layer.

16. The method of claim 15, wherein the bonding consists essentially of dielectric-to-dielectric bonding.

17. The method of claim 15, wherein the bonding includes bonding a first metallization pattern of the first substrate to a second metallization pattern of the second substrate.

18. The method of claim 15, wherein the forming the via includes forming the via extending into the first substrate.

19. The method of claim 15, wherein the forming the PPI structure includes forming the PPI structure with openings through the PPI structure.

20. The method of claim 15 further comprising forming a contact bump electrically coupled to the PPI structure.

21. A method comprising:

bonding a first substrate to a second substrate, the first substrate comprising a semiconductor substrate and an interconnect structure, the interconnect structure being on a first side of the semiconductor substrate, the interconnect structure being disposed between the semiconductor substrate and the second substrate after the bonding;

forming a conductive pad on a second side of the semiconductor substrate opposite from the first side of the semiconductor substrate, the conductive pad being electrically coupled to the interconnect structure;

forming a passivation layer on the conductive pad and on the second side of the semiconductor substrate;

forming a first stress buffer layer on the passivation layer;

forming an interconnect structure on the first stress buffer layer and through an opening through the first stress buffer layer and the passivation layer to the conductive pad; and

forming a second stress buffer layer on the interconnect structure and the first stress buffer layer.

22. The method of claim 21 further comprising forming a through via extending from the second side of the semiconductor substrate through the semiconductor substrate at least to the interconnect structure, the conductive pad being electrically coupled to the through via.

23. The method of claim 22, wherein the through via further extends into the second substrate.

24. The method of claim 21 further comprising forming an external electrical connector on the second stress buffer layer, through an opening through the second stress buffer layer, and contacting the interconnect structure.

25. The method of claim 24, wherein openings are through the interconnect structure in a region of the interconnect structure, the external electrical connector contacting the region of the interconnect structure.

26. The method of claim 21, wherein each of the first stress buffer layer and the second stress buffer layer has a Young'"'"'s modulus in a range from 2 GPa to 4 GPa, and a tensile strength in a range from 90 MPa to 200 MPa.

27. A method comprising:

bonding a first substrate to a second substrate, the first substrate comprising a first semiconductor substrate and a first interconnect structure on the first semiconductor substrate, the second substrate comprising a second semiconductor substrate and a second interconnect structure on the second semiconductor substrate, wherein after the bonding, the first interconnect structure and the second interconnect structure are disposed between the first semiconductor substrate and the second semiconductor substrate;

forming a through via extending from a side of the first semiconductor substrate opposite from the first interconnect structure through the first semiconductor substrate at least to the first interconnect structure;

forming a pad on the side of the first semiconductor substrate opposite from the first interconnect structure, the pad being electrically coupled to the through via;

forming a passivation layer on the pad and the first semiconductor substrate opposite from the first interconnect structure;

forming a first stress buffer layer on the passivation layer, the passivation layer being disposed between the first stress buffer layer and the first semiconductor substrate;

forming a post-passivation interconnect (PPI) structure on the first stress buffer layer, the PPI structure extending through an opening through the first stress buffer layer and the passivation layer to be electrically coupled to the pad;

forming a second stress buffer layer on the PPI structure and the first stress buffer layer, the PPI structure being disposed at least in part between the first stress buffer layer and the second stress buffer layer; and

forming an external electrical connection structure through an opening of the second stress buffer layer and contacting the PPI structure.

28. The method of claim 27, wherein the through via extends into the second interconnect structure.

29. The method of claim 27, wherein the via does not extend into the second interconnect structure.

30. The method of claim 27, wherein a first dielectric layer of the first substrate is bonded to a second dielectric layer of the second substrate during the bonding, no metal pattern being in a bonding surface of the first dielectric layer during the bonding, and no metal pattern being in a bonding surface of the second dielectric layer during the bonding.

31. The method of claim 27, wherein the PPI structure has PPI openings in a region where the external electrical connection structure contacts the PPI structure, the second stress buffer layer being at least partially disposed in the PPI openings.

32. The method of claim 27, wherein the external electrical connection structure comprises:

an under-bump structure contacting the PPI structure and on a surface of the second stress buffer layer distal from the first stress buffer layer, the under-bump structure being through the opening of the second stress buffer layer; and

a bump contact on the under-bump structure.

33. The method of claim 27, wherein each of the first stress buffer layer and the second stress buffer layer has a Young'"'"'s modulus in a range from 2 GPa to 4 GPa, and a tensile strength in a range from 90 MPa to 200 MPa.

34. The method of claim 27, wherein each of the first stress buffer layer and the second stress buffer layer is capable of elongation at least 30% before rupture.