VERTICAL NANOWIRE TRANSISTOR FOR INPUT/OUTPUT STRUCTURE

• US 20160049391A1
• Filed: 10/27/2015
• Published: 02/18/2016
• Est. Priority Date: 12/18/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: COLINGE, JEAN-PIERRE, DIAZ, CARLOS H., GUO, TA-PEN
• Granted Patent: US 9,735,146 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An electrostatic discharge (ESD) protection circuit includes an input terminal, a transistor, and an output terminal. The input terminal is configured to receive an input signal. The transistor includes a first source/drain region, a second source/drain region, and a drift region that has a resistance in series between the first and second source/drain regions and that is configured to attenuate an ESD voltage in the input signal. The output terminal is connected to the second source/drain region.

Claims

1. An electrostatic discharge (ESD) protection circuit comprising:

an input terminal configured to receive an input signal;

a first transistor including a first source/drain region, a second source/drain region, and a first drift region that has a resistance in series between the first and second source/drain regions and that is configured to attenuate an ESD voltage in the input signal; and

an output terminal connected to the second source/drain region.

2. The circuit of claim 1, wherein the first transistor further includes a nanowire that connects the first and second source/drain regions and a gate region that surrounds the nanowire, wherein the first drift region is a portion of the nanowire disposed between the gate region and the first source/drain region.

3. The circuit of claim 2, further comprising:

a substrate; and

a first well formed in the substrate, wherein the second source/drain region has a portion formed in the first well and a PN junction is formed between the first well and the second source/drain region and is configured to attenuate the ESD voltage in the input signal.

4. The circuit of claim 3, further comprising a second transistor including a first source/drain region, a second source/drain region connected to the output terminal, and a second drift region that has a resistance in series between the first and second source/drain regions of the second transistor and that is configured to attenuate the ESD voltage in the input signal.

5. The circuit of claim 4, wherein the second transistor further includes a nanowire that connects the first and second source/drain regions thereof and a gate region that surrounds the nanowire thereof, wherein the second drift region is a portion of the nanowire of the second transistor disposed between the gate region and the first source/drain region of the second transistor.

6. The circuit of claim 5, further comprising a second well formed in the substrate, wherein the second source/drain region of the second transistor has a portion formed in the second well and a PN junction is formed between the second well and the second source/drain region of the second transistor and is configured to attenuate the ESD voltage in the input signal.

7. The circuit of claim 6, wherein the input terminal is connected to the first source/drain regions of the first and second transistors.

8. The circuit of claim 6, wherein the input terminal is connected to the second source/drain regions of the first and second transistors.

9. The circuit of claim 6, wherein the input terminal is connected to the gate regions of the first and second transistors.

10. The circuit of claim 6, wherein the gate region of the first transistor is connected to the second well and the gate region of the second transistor is connected to the first well.

11. The circuit of claim 6, wherein the first source/drain region of the first transistor is connected to the first well and the first source/drain region of the second transistor is connected to the second well.

12. The circuit of claim 6, further comprising a third transistor including a first source/drain region, a second source/drain region, and a third drift region that has a resistance in series between the first and second source/drain regions thereof and that is configured to attenuate the ESD voltage in the input signal.

13. The circuit of claim 12, wherein the input terminal is connected to the first source/drain regions of the first and second transistors and the second source/drain region of the third transistor.

14. The circuit of claim 12, wherein the third transistor further includes a nanowire that connects the first and second source/drain regions thereof and a gate region that surrounds the nanowire thereof, wherein the third drift region is a portion of the nanowire of the third transistor disposed between the gate region and the first source/drain region of the third transistor.

15. The circuit of claim 14, further comprising a third well formed in the substrate, wherein the second source/drain region of the third transistor has a portion formed in the third well and a PN junction is formed between the third well and the second source/drain region of the third transistor and is configured to attenuate the ESD voltage in the input signal.

16. The circuit of claim 15, wherein the gate region of the first transistor is connected to the gate region of the third transistor and the second well, and the gate region of the second transistor is connected to the first well and the third well.

17. The circuit of claim 15, wherein the gate region of the second transistor is connected to the gate region of the third transistor and the first well, and the gate region of the first transistor is connected to the second well and the third well.

18. The circuit of claim 2, wherein the first transistor further includes a second drift region that has a resistance in series with the first drift region, that is configured to attenuate the ESD voltage in the input signal, and that is a portion of the nanowire disposed between the gate region and the second source/drain region.

19. A system comprising:

an electrostatic discharge (ESD) protection circuit including

an input terminal configured to receive an input signal,

a transistor including source and drain regions and a drift region that has a resistance in series between the source and drain regions and that is configured to attenuate an ESD voltage in the input signal, and

an output terminal connected to one of the source and drain regions; and

a protected circuit connected to the output terminal.

20. A method comprising:

receiving an input signal; and

attenuating an electrostatic discharge (ESD) voltage in the input signal by a drift region of a transistor that has a resistance in series between source and drain regions of the transistor.