SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

• US 20160049423A1
• Filed: 04/24/2015
• Published: 02/18/2016
• Est. Priority Date: 08/12/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Chaeho Kim, Dongchul Yoo, Jaeyoung Ahn, Woong Lee
• Inventors: YOO, Dongchul, AHN, Jaeyoung, LEE, Woong, KIM, Chaeho
• Granted Patent: US 9,536,897 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A three-dimensional semiconductor device may include a substrate including a cell array region, a word line contact region, and a peripheral circuit region, gate electrodes stacked on the substrate to extend from the cell array region to the word line contact region, a channel hole penetrating the gate electrodes on the cell array region and exposing an active region of the substrate, a dummy hole penetrating the gate electrodes on the word line contact region and exposing a device isolation layer provided on the substrate, and a semiconductor pattern provided in the channel hole but not in the dummy hole.

Claims

1. A three-dimensional semiconductor device, comprising:

a substrate including a cell array region, a word line contact region, and a peripheral circuit region;

gate electrodes stacked on the substrate to extend from the cell array region to the word line contact region;

a vertical channel structure penetrating the gate electrodes on the cell array region and being electrically connected to the substrate;

a semiconductor pattern disposed between the vertical channel structure and the substrate; and

a dummy pillar penetrating the gate electrodes on the word line contact region and being electrically separated from the substrate,

wherein the dummy pillar is provided to penetrate a lowermost one of the gate electrodes.

2. The device of claim 1, wherein the substrate comprises a first substrate and a second substrate, and the first substrate is disposed below the second substrate.

3. The device of claim 2, wherein the first substrate comprises the peripheral circuit region, and the second substrate comprises the cell array region and the word line contact region.

4. The device of claim 1, wherein the peripheral circuit region comprises a horizontal transistor.

5. The device of claim 1, wherein horizontal lengths of the gate electrodes decrease with increasing distance from the substrate.

6. The device of claim 1, wherein the vertical channel structure comprises a gate dielectric pattern, a vertical channel pattern, and an insulating gap-fill pattern.

7. The device of claim 6, wherein the gate dielectric pattern has a pipe-shaped structure.

8. The device of claim 6, wherein the gate dielectric pattern comprises a charge blocking layer, a charge storing layer, and a tunnel insulating layer.

9. The device of claim 6, wherein the vertical channel pattern has a hollow cylindrical shape or a cup shape.

10. The device of claim 6, wherein the vertical channel pattern is in direct contact with the semiconductor pattern.

11. The device of claim 1, wherein the dummy pillar is in contact with a device isolation layer provided on the word line contact region.

12. The device of claim 1, wherein the dummy pillar comprises a gate dielectric pattern, a vertical channel pattern, and an insulating gap-fill pattern.

13. The device of claim 1, wherein the vertical channel structure has a bottom surface positioned at a higher level than a bottom surface of the dummy pillar.

14. The device of claim 1, wherein the semiconductor pattern penetrates the lowermost one of the gate electrodes and is in contact with the substrate.

15. The device of claim 1, further comprising:

interconnection plugs electrically connected to the gate electrodes.

16. The device of claim 15, wherein the interconnection plugs have different vertical lengths from each other.

17. A three-dimensional semiconductor device, comprising:

a substrate including a cell array region, a word line contact region, and a peripheral circuit region;

gate electrodes stacked on the substrate to extend from the cell array region to the word line contact region;

a channel hole penetrating the gate electrodes on the cell array region and exposing an active region of the substrate;

a dummy hole penetrating the gate electrodes on the word line contact region and exposing a device isolation layer provided on the substrate; and

a semiconductor pattern provided in the channel hole but not in the dummy hole.

18. The device of claim 17, wherein the substrate comprises a first substrate and a second substrate, and the first substrate is provided below the second substrate.

19. The device of claim 18, wherein the first substrate comprises the peripheral circuit region, and the second substrate comprises the cell array region and the word line contact region.

20. A three-dimensional semiconductor device, comprising:

a substrate including a cell array region and a word line contact region;

gate electrodes stacked on the substrate to extend from the cell array region to the word line contact region;

a channel hole penetrating the gate electrodes on the cell array region and exposing an active region of the substrate;

a dummy hole penetrating the gate electrodes on the word line contact region and exposing a device isolation layer provided on the substrate;

a semiconductor pattern and a vertical channel structure provided in the channel hole; and

a dummy pillar provided in the dummy hole, wherein the dummy pillar has a bottom surface positioned at a lower level than a bottom surface of the vertical channel structure.