INTEGRATED CIRCUITS WITH SELF ALIGNED CONTACT STRUCTURES FOR IMPROVED WINDOWS AND FABRICATION METHODS

• US 20160049427A1
• Filed: 08/18/2014
• Published: 02/18/2016
• Est. Priority Date: 08/18/2014
• Status: Active Grant

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: GlobalFoundries, Inc.
• Inventors: ZANG, Hui
• Granted Patent: US 9,356,047 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/32115 Planarisation
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Devices and methods for forming semiconductor devices with self aligned contacts for improved process windows are provided. One method includes, for instance: obtaining a wafer with at least two gates, forming partial spacers adjacent to the at least two gates, and forming at least one contact on the wafer. One intermediate semiconductor device includes, for instance: a wafer with an isolation region, at least two gates disposed on the isolation region, at least one source region disposed on the isolation region, at least one drain region disposed on the isolation region, and at least one contact positioned between the at least two gates, wherein a first portion of the at least one contact engages the at least one source region or the at least one drain region and a second portion of the at least one contact extends above a top surface of the at least two gates.

Claims

1. A method comprising:

obtaining a wafer with at least two gates;

forming partial spacers adjacent to the at least two gates, wherein forming the partial spacers comprises;

etching into an oxide layer between the at least two gates;

depositing a spacer layer over the wafer; and

etching the spacer layer to form the partial spacers; and

forming at least one contact on the wafer;

depositing a second oxide layer over the wafer after forming the partial spacers; and

performing planarization to the second oxide layer.

4. The method of claim 1, wherein forming the at least one contact comprises:

depositing an interlayer dielectric layer over the wafer;

applying a photoresist layer;

patterning the photoresist layer;

etching into the interlayer dielectric layer, the second oxide layer, and the oxide layer between the partial spacers to form at least one cavity;

removing the photoresist layer;

depositing at least one contact material over the wafer and into the at least one cavity; and

performing planarization to the wafer to remove excess contact material to form the at least one contact.

5. The method of claim 4, further comprising:

etching to remove the partial spacers before depositing the at least one contact material.

12. The method of claim 1, further comprising:

forming a self-aligned contact over each of the at least two gates.

2. (canceled)

3. (canceled)

6. A method comprising:

obtaining a wafer with at least two gates;

forming partial spacers adjacent to the at least two gates, wherein forming the partial spacers comprises;

etching into an oxide layer between the at least two gates;

depositing a spacer layer over the wafer; and

etching the spacer layer to form the partial spacers; and

forming at least one contact on the wafer, wherein forming the at least one contact comprises;

forming at least one cavity between the partial spacers;

depositing at least one contact material over the wafer and into the at least one cavity; and

performing planarization to the wafer to remove excess contact material to form the at least one contact.

7. The method of claim 6, wherein forming the at least one contact further comprises:

depositing a second oxide layer over the wafer after planarization of the contact material;

patterning the second oxide layer;

depositing a second layer of the at least one contact material; and

performing planarization to the wafer to remove excess contact material to form the at least one contact.

8. The method of claim 6, wherein forming the at least one contact further comprises:

etching to remove the partial spacers before depositing the at least one contact material.

9. The method of claim 6, wherein forming the at least one cavity between the partial spacers comprises:

etching directly into the interlayer dielectric layer and the oxide layer to form the at least one cavity.

10. The method of claim 6, wherein forming the at least one cavity between the partial spacers comprises:

applying a photoresist layer over the wafer;

patterning the photoresist layer;

etching into the interlayer dielectric layer and the oxide layer to form the at least one cavity.

11. The method of claim 6, wherein forming the at least one cavity between the partial spacers comprises:

depositing a second oxide layer over the wafer;

performing planarization to the second oxide layer;

applying a photoresist layer over the wafer;

patterning the photoresist layer; and

etching into the interlayer dielectric layer and the oxide layer to form the at least one cavity.

13. An intermediate semiconductor device comprising:

a wafer with an isolation region;

at least two gates disposed on the isolation region;

at least one source region disposed on the isolation region;

at least one drain region disposed on the isolation region;

at least one contact positioned between the at least two gates;

at least two spacers, wherein a spacer is positioned adjacent each side of the at least two gates; and

at least two partial spacers, wherein a partial spacer is positioned adjacent each of the at least two spacers;

wherein a first portion of the at least one contact engages the at least one source region or the at least one drain region and a second portion of the at least one contact extends above a top surface of the at least two gates.

14. The device of claim 13, wherein the second portion extends from the top surface of the at least two gates to a position above the top surface of the at least two gates.

15. The device of claim 13, wherein the second portion extends from a position below the top surface of the at least two gates to a position above the top surface of the at least two gates.

16. The device of claim 13, wherein the first portion has a first width and the second portion has a second width, wherein the first width is smaller than the second width.

17. The device of claim 13, further comprising:

at least two self-aligned contacts are positioned over the at least two gates and between the at least two spacers.

18. (canceled)

19. The device of claim 19, wherein the partial spacer extends from a top surface of the at least two spacers partially down toward the isolation region.

20. The device of claim 19, wherein the at least two self-aligned contacts have a self-aligned contact length and the partial spacers have a partial spacer length, the partial spacer length is less than the self-aligned contact length.