CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME

• US 20160049436A1
• Filed: 08/05/2015
• Published: 02/18/2016
• Est. Priority Date: 08/13/2014
• Status: Active Grant

• Current Assignee: Xintec Incorporated
• Original Assignee: Xintec Incorporated
• Inventors: LIN, Chia-Sheng, CHANG, Yi-Ming, LIN, Po-Shen
• Granted Patent: US 9,881,959 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14685 Process for coatings or optical elements
• CPC Class Codes: H01L 27/14687 Wafer level processing

Abstract

A method of manufacturing chip package includes providing a semiconductor substrate having at least a photo diode and an interconnection layer. The interconnection layer is disposed on an upper surface of the semiconductor substrate and above the photo diode and electrically connected to the photo diode. At least a redistribution circuit is formed on the interconnection layer. The redistribution circuit is electrically connected to the interconnection layer. A packaging layer is formed on the redistribution circuit. Subsequently, a carrier substrate is attached to the packaging layer. A colour filter is formed on a lower surface of the semiconductor substrate. A micro-lens module is formed under the colour filter. The carrier substrate is removed.

Claims

1. A method of manufacturing chip package, comprising:

providing a semiconductor substrate having at least a photo diode and an interconnection layer disposed on an upper surface of the semiconductor substrate, the interconnection layer being above the photo diode and electrically connected to the photo diode;

forming at least a redistribution circuit on the interconnection layer, the redistribution circuit electrically connected to the interconnection layer;

forming a packaging layer on the redistribution circuit;

attaching a carrier substrate to the packaging layer;

forming a colour filter on a lower surface of the semiconductor substrate;

forming a micro-lens module under the colour filter; and

removing the carrier substrate.

2. The method of manufacturing chip package of claim 1, wherein before forming the colour filter under the semiconductor substrate further comprises:

thinning the semiconductor substrate from the lower surface towards the upper surface.

3. The method of manufacturing chip package of claim 2, wherein thinning the semiconductor substrate from the lower surface towards the upper surface is conducted by mechanical polishing, chemical base etching, chemical mechanical polishing or the combination thereof.

4. The method of manufacturing chip package of claim 1, wherein after forming the redistribution circuit on the interconnection layer further comprises:

forming an anti-reflection layer on the interconnection layer.

5. The method of manufacturing chip package of claim 4, wherein forming the anti-reflection layer on the interconnection layer further comprises:

depositing a dielectric layer covering the redistribution circuit and the interconnection layer;

depositing a metal layer covering the dielectric layer; and

photolithographing the dielectric layer and the metal layer to expose the redistribution circuit.

6. The method of manufacturing chip package of claim 5, wherein the dielectric layer includes silicon oxide, and the metal layer includes silver.

7. The method of manufacturing chip package of claim 1, wherein forming a packaging layer on the redistribution circuit further comprises:

forming a packaging layer covering the redistribution circuit and the interconnection layer; and

forming an opening on the packaging layer, the opening exposing a portion of the redistribution circuit.

8. The method of manufacturing chip package of claim 7, wherein the opening is formed by laser drilling.

9. The method of manufacturing chip package of claim 7 further comprising:

forming a soldering ball on the packaging layer, a portion of the soldering ball disposed on the opening to be electrically connected to the redistribution circuit.

10. The method of manufacturing chip package of claim 9, wherein soldering ball includes tin.

11. The method of manufacturing chip package of claim 7 further comprising:

forming a soldering wire, one end of the soldering wire disposed on the opening to be electrically connected to the redistribution circuit.

12. The method of manufacturing chip package of claim 1, wherein the redistribution circuit includes aluminium, copper, nickel or an alloy thereof.

13. A chip package, comprising:

a semiconductor substrate having at least a photo diode and an interconnection layer disposed on an upper surface of the semiconductor substrate, the interconnection layer being above the photo diode and electrically connected to the photo diode;

at least a redistribution circuit disposed on the interconnection layer, the redistribution circuit electrically connected to the interconnection layer;

a packaging layer disposed on the redistribution circuit, the packaging layer formed with an opening to expose a portion of the redistribution circuit;

a colour filter disposed on a lower surface of the semiconductor substrate; and

a micro-lens module disposed under the colour filter.

14. The chip package of claim 13 further comprising:

a soldering ball disposed on the packaging layer, a portion of the soldering ball over the opening and electrically connected to the redistribution circuit.

15. The chip package of claim 14, wherein the soldering ball includes tin.

16. The chip package of claim 13 further comprising:

a soldering wire disposed on the opening and electrically connected to the redistribution circuit.

17. The chip package of claim 13 further comprising:

an anti-reflection layer disposed on the interconnection layer.

18. The chip package of claim 17, wherein the anti-reflection layer includes:

a dielectric layer disposed on a side of the redistribution circuit and on the interconnection layer; and

a metal layer disposed on the dielectric layer.

19. The chip package of claim 18, wherein the dielectric layer includes silicon oxide, and the metal layer includes silver.

20. The chip package of claim 13 further comprising:

an optical glass disposed under the micro-lens module; and

a glue attachment layer sandwiched between the micro-lens module and the optical glass.