VARIABLE CHANNEL STRAIN OF NANOWIRE TRANSISTORS TO IMPROVE DRIVE CURRENT

• US 20160049472A1
• Filed: 10/27/2015
• Published: 02/18/2016
• Est. Priority Date: 06/20/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: YU, TSUNG-HSING, HSU, YEH, LIU, CHIA-WEN, COLINGE, JEAN-PIERRE
• Granted Patent: US 9,728,602 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28017 the insulator being formed after the semiconductor body, the semiconductor being silicon
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate

Abstract

A semiconductor device includes a nanowire structure and a stressor. The nanowire structure includes a first channel section and a second channel section. The stressor subjects the first channel section to a first strain level and the second channel section to a second strain level greater than the first strain level. The difference between the second strain level and the first strain level is less than the second strain level.

Claims

1. A semiconductor device comprising:

a nanowire structure including a first channel section and a second channel section; and

a stressor subjecting the first channel section to a first strain level and the second channel section to a second strain level greater than the first strain level, wherein the difference between the second strain level and the first strain level is less than the second strain level.

2. The semiconductor device of claim 1, further comprising a gate region, wherein the stressor is disposed between the gate region and the nanowire structure.

3. The semiconductor device of claim 2, wherein the stressor surrounds the nanowire structure and the gate region surrounds the stressor.

4. The semiconductor device of claim 1, further comprising a gate region disposed between the stressor and the nanowire structure.

5. The semiconductor device of claim 4, wherein the gate region surrounds the nanowire structure and the stressor surrounds the gate region.

6. The semiconductor device of claim 1, wherein the nanowire structure further includes a third channel section and the stressor further subjects the third channel section to a third strain level different from the first and second strain levels.

7. A method comprising:

providing a semiconductor device that includes a nanowire structure; and

subjecting a first channel section of the nanowire structure to a first strain level and a second channel section of the nanowire structure to a second strain level greater than the first strain level, wherein the difference between the second strain level and the first strain level is less than the second strain level.

8. The method of claim 7, wherein the subjecting a first channel section of the nanowire structure to a first strain level and a second channel section of the nanowire structure to a second strain level includes

forming a stressor on the nanowire structure, and

forming a gate region on the stressor.

9. The method of claim 8, wherein the forming a stressor on the nanowire structure includes surrounding the nanowire structure with the stressor and the forming a gate region on the stressor includes surrounding the stressor with the gate region.

10. The method of claim 7, wherein the subjecting a first channel section of the nanowire structure to a first strain level and a second channel section of the nanowire structure to a second strain level includes

forming a gate region on the nanowire structure, and

forming a stressor on the gate region.

11. The method of claim 10, wherein the forming a gate region on the nanowire structure includes surrounding the nanowire structure with the gate region and the forming a stressor on the gate region includes surrounding the gate region with the stressor.

12. The method of claim 7, further comprising subjecting a third channel section of the nanowire structure to a third strain level different from the first and second strain levels.

13. A semiconductor device comprising:

a source/drain region;

a stressor at least a portion of which is disposed in the source/drain region; and

a nanowire structure extending from the stressor, wherein the stressor subjects the nanowire structure to a strain level.

14. The semiconductor device of claim 13, wherein the stressor includes silicon and germanium.

15. The semiconductor device of claim 13, wherein the stressor includes silicon, carbon, and phosphorus.

16. The semiconductor device of claim 13, wherein the stressor includes a pair of layers, one of which is formed on the other and one of which has a greater concentration of boron than the other.

17. The semiconductor device of claim 13, wherein the stressor includes a pair of layers, one of which is formed on the other and one of which has a greater percentage of germanium than the other.

18. The semiconductor device of claim 13, wherein the stressor includes a pair of layers, one of which is formed on the other and one of which has a greater concentration of phosphorus than the other.

19. The semiconductor device of claim 13, wherein the stressor includes a pair of layers, one of which is formed on the other and one of which has a greater percentage of carbon than the other.

20. The semiconductor device of claim 13, further comprising a substrate, wherein at least a portion of the source/drain region is disposed in the substrate.