SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20160049478A1
• Filed: 04/03/2015
• Published: 02/18/2016
• Est. Priority Date: 08/18/2014
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Song, Moon-Kyun, Kim, Weon-Hong, Choi, Soo-Jung, Hwang, Yoon-Tae
• Application Number:
  US14/678,331
• Publication Number:
  US 20160049478A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for fabricating a semiconductor device comprises forming a gate insulation layer on a substrate including a first region and a second region, forming a first gate conductive layer and a capping layer on the first region and the second region and heat-treating the substrate, removing the capping layer from the first region and the second region, forming a second gate conductive layer on the first region and the second region, nitriding the second gate conductive layer, and forming a third gate conductive layer on the second region.

Claims

1. A method for fabricating a semiconductor device, the method comprising:

forming a gate insulation layer on a substrate including a first region and a second region;

forming a first gate conductive layer and a capping layer on the first region and the second region and heat-treating the substrate;

removing the capping layer from the first region and the second region;

forming a second gate conductive layer on the first region and the second region;

nitriding the second gate conductive layer; and

forming a third gate conductive layer on the second region.

2. The method of claim 1, wherein the step of removing the capping layer from the first region and the second region further comprises removing the first gate conductive layer from the first region and the second region.

3. The method of claim 2, wherein the step of forming the gate insulation layer on the substrate comprises:

forming an interface layer on the substrate; and

forming a high-k gate insulation layer on the interface layer,

wherein the second gate conductive layer direct contacts the high-k gate insulation layer.

4. The method of claim 1, wherein the step of forming the gate insulation layer on the substrate comprises:

forming a first trench and a second trench on the first region and the second region, respectively; and

forming the gate insulation layer along lateral surfaces and bottom surfaces of the first trench and the second trench.

5. The method of claim 4, wherein the forming of the third gate conductive layer on the second region comprises:

forming the third gate conductive layer on the second gate conductive layer of the first region and the second region;

forming a mask pattern on the second region; and

removing the second gate conductive layer from the first region using the mask pattern.

6. The method of claim 1, wherein the step of nitriding the second gate conductive layer is performed using a gas including ammonia (NH₃) or plasma-state ammonia (NH₃).

7. The method of claim 6, wherein the step of nitriding the second gate conductive layer using the gas including ammonia (NH₃) is performed at a temperature ranging from about 500°

C. to about 700°

C.

8. The method of claim 6, wherein the step of nitriding the second gate conductive layer using the plasma-state ammonia (NH₃) is performed at a temperature ranging from about 25°

C. to about 400°

C.

9. The method of claim 1, wherein the second gate conductive layer comprises a TaN layer.

10. A method for fabricating a semiconductor device, the method comprising:

forming a gate insulation layer on a substrate including a first region and a second region;

forming a first gate conductive layer and a capping layer on the first region and the second region and heat-treating the substrate;

removing the first gate conductive layer and the capping layer from the first region and the second region;

forming a second gate conductive layer on the first region and the second region;

forming a third gate conductive layer on the second region; and

nitriding the second gate conductive layer of the first region.

11. The method of claim 10, wherein the step of nitriding the second gate conductive layer of the first region comprises implanting a gas including ammonia (NH₃) into the second gate conductive layer of the first region and third gate conductive layer of the second region.

12. The method of claim 11, wherein the second gate conductive layer of the first region is exposed to the gas including ammonia (NH₃) and the second gate conductive layer of the second region is not exposed to the gas including ammonia (NH₃).

13. The method of claim 10, after forming the second gate conductive layer on the first region and the second region, further comprising nitriding the second gate conductive layer.

14. A method for fabricating a semiconductor device, the method comprising:

forming a first fin type active pattern and a second fin type active pattern on a substrate;

forming a first trench crossing the first fin type active pattern on the first fin type active pattern and forming a second trench crossing the second fin type active pattern on the second fin type active pattern;

forming a first TaN layer along lateral surfaces and a bottom surface of the first trench and forming a second TaN layer along lateral surfaces and a bottom surface of the second trench;

implanting a nitride gas on the first TaN layer and the second TaN layer;

forming a TiN layer on the second TaN layer; and

implanting a nitride gas on the first TaN layer and the TiN layer.

15. The method of claim 14, wherein the nitride gas includes ammonia (NH₃).

16-20. -20. (canceled)