INTEGRATED CIRCUITS WITH NANOWIRES AND METHODS OF MANUFACTURING THE SAME

• US 20160049489A1
• Filed: 08/12/2014
• Published: 02/18/2016
• Est. Priority Date: 08/12/2014
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Wan, Jing, Bouche, Guillaume, Wei, Andy, Koh, Shao Ming
• Granted Patent: US 9,306,019 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a layered fin overlying a substrate, where the layered fin includes an SiGe layer and an Si layer. The SiGe layer and the Si layer alternate along a height of the layered fin. A dummy gate is formed overlying the substrate and the layered fin, and a source and a drain area formed in contact with the layered fin. The dummy gate is removed to expose the SiGe layer and the Si layer, and the Si layer is removed to produce an SiGe nanowire. A high K dielectric layer that encases the SiGe nanowire between the source and the drain is formed, and a replacement metal gate is formed so that the replacement metal gate encases the high K dielectric layer and the SiGe nanowire between the source and drain.

Claims

1. A method of manufacturing an integrated circuit comprising:

forming a layered fin overlying a substrate, wherein the layered fin comprises an SiGe layer and an Si layer, wherein the SiGe layer and the Si layer alternate along a height of the layered fin;

forming a gate barrier layer overlying the layered fin and along a side of the layered fin;

forming a dummy gate overlying the substrate and the layered fin such that the gate barrier layer is positioned between the dummy gate and the layered fin;

forming a source and a drain that are in contact with the layered fin;

removing the dummy gate to expose the SiGe layer and the Si layer;

removing the gate barrier layer after removing the dummy gate;

removing the Si layer to produce an SiGe nanowire;

forming a high K dielectric layer encasing the SiGe nanowire between the source and the drain; and

forming a replacement metal gate encasing the high K dielectric layer and the SiGe nanowire between the source and the drain.

2. The method of claim 1 further comprising:

isolating the layered fin for an nFET before removing the Si layer to produce the SiGe nanowire;

exposing the layered fin for the nFET after removing the Si layer to produce the SiGe nanowire;

isolating the SiGe nanowire;

removing the SiGe layer of the layered fin for the nFET to produce an Si nanowire;

wherein forming the high K dielectric layer comprises forming the high K dielectric layer encasing the SiGe nanowire between the source and the drain, and forming the high K dielectric layer encasing the Si nanowire between the source and the drain; and

wherein forming the replacement metal gate comprises forming the replacement metal gate encasing the high K dielectric layer and the SiGe nanowire between the source and the drain, and forming the replacement metal gate encasing the high K dielectric layer and the Si nanowire between the source and the drain.

3. The method of claim 1 wherein forming the layered fin comprises forming a plurality of layered fins, the method further comprising:

forming an insulating layer between adjacent layered fins and overlying the substrate.

4. The method of claim 1 wherein forming the layered fin comprises forming the layered fin with a fin base, wherein the fin base extends over the substrate.

5. The method of claim 4 further comprising:

forming an STI insulator overlying the substrate and adjacent to the fin base; and

wherein forming the dummy gate comprises forming the dummy gate overlying the STI insulator.

6. The method of claim 1 further comprising:

forming spacers on a side of the dummy gate; and

wherein removing the dummy gate comprises retaining the spacers.

7. The method of claim 1 further comprising:

forming a layered stack overlying the substrate; and

wherein forming the layered fin comprises etching the layered stack and the substrate to form the layered fin such that the layered fin comprises a fin base of the same material as the substrate.

10. The method of claim 1 wherein forming the source and the drain comprises:

etching a portion of the layered fin to form a source cavity and a drain cavity; and

epitaxially growing the source and the drain in the source cavity and the drain cavity.

11. The method of claim 10 wherein epitaxially growing the source and the drain comprises epitaxially growing the source wherein the source and the drain are about 10 to about 50 mole percent germanium and about 50 to about 90 mole percent silicon.

8. (canceled)

9. (canceled)

12. A method of manufacturing an integrated circuit comprising:

forming a layered stack overlying a substrate;

forming a layered fin overlying a fin base, wherein the layered fin comprises an SiGe layer and an Si layer, wherein the SiGe layer and the Si layer alternate along a height of the layered fin, wherein the fin base extends over the substrate, and wherein forming the layered fin comprises etching the layered stack and the substrate to form the layered fin such that the fin base is formed of the same material as the substrate;

forming a gate barrier layer overlying the layered fin and along a side of the layered fin;

forming a dummy gate overlying the layered fin and the substrate such that the gate barrier layer is positioned between the dummy gate and the layered fin;

forming a source and a drain contacting the layered fin, wherein the source and the drain overlie the fin base;

forming an insulating layer overlying the substrate and adjacent to the dummy gate;

removing the dummy gate to expose a portion of the layered fin;

removing the gate barrier layer after removing the dummy gate; and

forming an Si nanowire from the layered fin, where the Si nanowire is suspended between the source and the drain.

13. The method of claim 12 further comprising:

isolating the layered fin for a pFET before forming the Si nanowire;

exposing the layered fin for the pFET after forming the Si nanowire;

isolating the Si nanowire; and

forming an SiGe nanowire from the layered fin for the pFET.

15. The method of claim 12 wherein forming the source and the drain comprises:

etching a portion of the layered fin to form a source cavity and a drain cavity; and

epitaxially growing the source and the drain in the source cavity and the drain cavity, respectively.

16. The method of claim 12 further comprising:

forming a high K dielectric layer encasing the Si nanowire between the source and the drain; and

forming a replacement metal gate encasing the high K dielectric layer and the Si nanowire between the source and the drain.

18. The method of claim 12 wherein forming the Si nanowire comprises selectively etching the SiGe layer to form the Si nanowire from the Si layer.

19. The method of claim 12 further comprising:

forming spacers on a side of the dummy gate; and

wherein removing the dummy gate comprises retaining the spacers.

14. (canceled)

17. (canceled)

20. (canceled)

21. A method of manufacturing an integrated circuit comprising:

forming a layered fin overlying a substrate, wherein the layered fin comprises an SiGe layer and an Si layer, wherein the SiGe layer and the Si layer alternate along a height of the layered fin;

forming a dummy gate overlying the substrate and the layered fin;

forming a source and a drain that are in contact with the layered fin;

removing the dummy gate to expose the SiGe layer and the Si layer;

isolating the layered fin for an nFET, wherein the nFET comprises an SiGe nanowire;

removing the Si layer to produce the SiGe nanowire;

exposing the layered fin for the nFET after removing the Si layer to produce the SiGe nanowire;

isolating the SiGe nanowire;

removing the SiGe layer of the layered fin for the nFET to produce an Si nanowire;

forming a high K dielectric layer encasing the SiGe nanowire between the source and the drain, and wherein the high K dielectric layer encases the Si nanowire between the source and the drain; and

forming a replacement metal gate encasing the high K dielectric layer and the SiGe nanowire between the source and the drain, and wherein the replacement metal gate encases the high K dielectric layer and the Si nanowire between the source and the drain.