FLASH MEMORY AND METHOD OF MANUFACTURING THE SAME

• US 20160049525A1
• Filed: 08/18/2014
• Published: 02/18/2016
• Est. Priority Date: 08/18/2014
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chen, Zhen, Wang, Shen-De, Ta, Wei, Chiu, Yi-Shan, Chang, Yuan-Hsiang, Liu, Weichang
• Granted Patent: US 9,660,106 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/31105 Etching inorganic layers
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A flash memory structure includes a memory gate on a substrate, a select gate adjacent to the memory gate, and an oxide-nitride spacer between the memory gate and the select gate, where the oxide-nitride spacer further includes an oxide layer and a nitride layer having an upper nitride portion and a lower nitride portion, and the upper nitride portion is thinner than the lower nitride portion.

Claims

1. A flash memory, comprising:

a memory gate on a substrate;

a select gate adjacent to said memory gate; and

an oxide-nitride spacer between said memory gate and said select gate, wherein said oxide-nitride spacer comprises an oxide layer and a nitride layer having an upper nitride portion and a lower nitride portion, a top surface of said upper nitride portion is higher than a top surface of said oxide layer, and said upper nitride portion is thinner than said lower nitride portion.

2. The flash memory of claim 1, further comprising a plane interface between said upper nitride portion and said lower nitride portion, wherein said plane is higher than the top surface of said memory gate.

3. The flash memory of claim 1, wherein a height of said oxide layer of said oxide-nitride spacer is flush with a top surface of said memory gate.

4. The flash memory of claim 1, wherein a thickness of said upper nitride portion is smaller than 60% of a thickness of said lower nitride portion.

5. The flash memory of claim 1, wherein a thickness of said upper nitride portion is smaller than 30 Angstroms.

6. The flash memory of claim 1, wherein a thickness of said lower nitride portion is larger than 40 Angstroms.

7. The flash memory of claim 1, wherein a height of said select gate is higher than a height of said memory gate.

8. The flash memory of claim 1, further comprising a gate dielectric layer between said memory gate and said substrate and between said select gate and said substrate.

9. The flash memory of claim 8, wherein said gate dielectric layer between said memory gate and said substrate is oxide/nitride/oxide tri-layer.

10. The flash memory of claim 1, wherein said nitride layer comprises silicon nitride (SiN) or silicon carbide nitride (SiCN).

11. The flash memory of claim 1, wherein said memory gate and said select gate comprise polysilicon.

17. The method of manufacturing a flash memory of claim 10, wherein said photoresist layer is an organic dielectric layer.

12. A method of manufacturing a flash memory, comprising the steps of:

providing a substrate;

forming a gate structure with a memory gate and a nitride hard mask on said memory gate;

forming an oxide-nitride spacer on the side of said memory gate;

covering a photoresist layer on said gate structure and said oxide-nitride spacer;

etching back said photoresist layer to expose the portion of said gate structure above said memory gate and thin the exposed nitride portion of said oxide-nitride spacer; and

forming a select gate on the side of said oxide-nitride spacer.

13. The method of manufacturing a flash memory of claim 12, wherein the step of forming said gate structure comprises:

forming an oxide-nitride-oxide tri-layer on said substrate;

forming a memory gate layer on said oxide-nitride-oxide tri-layer;

forming a nitride hard mask layer on said memory gate layer;

patterning said nitride hard mask layer into nitride hard mask; and

performing an etch process with said nitride hard mask to pattern said memory gate layer and said oxide-nitride-oxide tri-layer into gate structure.

14. The method of manufacturing a flash memory of claim 12, further comprising removing said photoresist layer after thinning exposed said nitride portion of said oxide-nitride spacer.

15. The method of manufacturing a flash memory of claim 12, further comprising removing said nitride hard mask after forming a select gate.

16. The method of manufacturing a flash memory of claim 15, wherein said nitride hard mask is removed by wet etching process using phosphoric acid.