ELECTRONIC DEVICE AND SEMICONDUCTOR PACKAGE WITH THERMALLY CONDUCTIVE VIA

• US 20160050744A1
• Filed: 08/14/2015
• Published: 02/18/2016
• Est. Priority Date: 08/14/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: HAN, Seok-jae, LEE, Eung-chang
• Granted Patent: US 9,674,940 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45139 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48147 with an intermediate bond, e.g. continuous wire daisy chain
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83224 using a laser
• CPC Class Codes: H01L 2224/83862 Heat curing
• CPC Class Codes: H01L 2224/83874 Ultraviolet [UV] curing
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/06506 : Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 23/3677 : Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 24/00 : Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/0781 : being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H05K 1/0206 : by printed thermal vias
• CPC Class Codes: H05K 1/113 : Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 1/115 : Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 2201/09345 : Power and ground in the same plane; Power planes for two voltages in one plane
• CPC Class Codes: H05K 2201/096 : Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 2201/10159 : Memory
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 2201/10969 : Metallic case or integral heatsink of component electrically connected to a pad on PCB

Abstract

An electronic device and semiconductor package include a printed circuit board and a semiconductor device mounted thereon. The printed circuit board includes one or more thermally conductive vias for dissipating heat.

Claims

1. A semiconductor package comprising:

a printed circuit board; and

a semiconductor device mounted on the printed circuit board,

wherein the printed circuit board comprises;

at least a first power or ground pattern layer formed in the printed circuit board;

at least a first power or ground pad formed on a bottom surface of the printed circuit board;

at least a first electrically conductive via that extends from the first power or ground pattern layer to the bottom surface of the printed circuit board to be connected to the first power or ground pad; and

at least a first thermally conductive via that extends from the power or ground pattern layer to a top surface of the printed circuit board to be exposed to the outside of the printed circuit board, wherein the thermally conductive via is disposed in a region overlapping the semiconductor device when seen in a plan view.

2. The semiconductor package of claim 1, further comprising either an adhesive layer or an underfill layer, disposed between the printed circuit board and the semiconductor device,

wherein a top surface of the thermally conductive via contacts the adhesive layer or the underfill layer.

3. The semiconductor package of claim 1, wherein the first thermally conductive via overlaps the first electrically conductive via when seen in a plan view.

4. The semiconductor package of claim 1, wherein the first thermally conductive via is disposed in a region overlapping the semiconductor device and the first power or ground pad when seen in a plan view.

5. The semiconductor package of claim 1, wherein:

the first thermally conductive via comprises a first sub thermally conductive via and a second sub thermally conductive via, a top surface of the first sub thermally conductive via being exposed to the outside of the printed circuit board, and a top surface of the second thermally conductive via coming into contact with the first sub thermally conductive via and a bottom surface thereof coming into contact with the first power or ground pattern layer, and

a width of the first sub thermally conductive via is greater than a width of the second sub thermally conductive via.

6. The semiconductor package of claim 1, wherein a material of the first thermally conductive via is different from a material of the first electrically conductive via.

7. The semiconductor package of claim 1, wherein a thermal conductivity of the first thermally conductive via is greater than a thermal conductivity of prepreg layers or a protection layer of the printed circuit board through which the first thermally conductive via passes.

8. The semiconductor package of claim 1, wherein the printed circuit board comprises at least a first signal pattern layer formed thereinside, and the first thermally conductive via is electrically insulated from the signal pattern layer.

9. The semiconductor package of claim 8, wherein:

the semiconductor device includes a stack of semiconductor chips mounted on the printed circuit board.

10. The semiconductor package of claim 1, wherein a top surface of the thermally conductive via is disposed at a same level as the top surface of the printed circuit board.

20. The semiconductor package of claim 1, wherein the heat dissipating via has one end electrically floating and one end electrically connected to a wiring distribution layer pattern electrically connected to the power pad or ground pad.

11. A semiconductor package, comprising:

a printed circuit board;

one or more semiconductor chips mounted on the printed circuit board, the one or more semiconductor chips including at least a first semiconductor chip adjacent to the printed circuit board; and

an intermediate layer formed between a bottom of the first semiconductor chip and a top of the printed circuit board,

wherein the printed circuit board includes;

a first ground pad electrically connected to circuitry of the first semiconductor chip and for providing ground voltage to the first semiconductor chip, and a first power pad electrically connected to circuitry of the first semiconductor chip for providing power voltage to the first semiconductor chip;

at least a first insulating layer of the printed circuit board contacting the intermediate layer; and

at least a first thermally conductive via passing through the first insulating layer, the thermally conductive via extending between the intermediate layer and one of the first ground pad and the first power pad, electrically and thermally connected to one of the first ground pad and the first power pad, and contacting the intermediate layer,

wherein the first thermally conductive via is disposed in a region overlapping the first semiconductor chip when seen in a plan view.

12. The semiconductor package of claim 11, wherein the electrically insulating layer is one of an underfill layer contacting the printed circuit board and the first semiconductor chip, or an adhesive layer contacting the printed circuit board and the first semiconductor chip.

13. The semiconductor package of claim 11, wherein the first insulating layer is a prepreg layer disposed on a core layer of the printed circuit board.

14. The semiconductor package of claim 11, wherein the first thermally conductive via is formed of a material different from the first insulating layer, and has a thermal conductivity greater than that of the first insulating layer.

15. The semiconductor package of claim 11, wherein the first thermally conductive via extends to the surface of the printed circuit board and is positioned to receive heat from the one or more semiconductor chips and dissipate the heat toward a bottom of the printed circuit board.

16. The semiconductor package of claim 11, wherein the first thermally conductive via vertically overlaps an electrically conductive through via connected to the first ground pad or first power pad.

17. The semiconductor package of claim 16, wherein the first thermally conductive via contacts the intermediate layer at a top surface of the printed circuit board, and the electrically conductive through via connects to the first ground pad or first power pad at a bottom of the printed circuit board.

18. The semiconductor package of claim 11, wherein the one or more semiconductor chips includes a plurality of semiconductor chips.

19. (canceled)

21. An electronic device comprising:

a first semiconductor chip;

a printed circuit board on which the first semiconductor chip is mounted, and including;

a top surface and a bottom surface opposite the top surface, wherein an insulating layer of the printed circuit board is located at a top of the printed circuit board, and

a first power pad electrically connected to circuitry of the first semiconductor chip for providing power voltage to the first semiconductor chip; and

a first thermally conductive via electrically connected to the first power pad, extending to the top surface of the printed circuit board, and positioned to receive heat from the first semiconductor chip and dissipate the heat toward the first power pad, the first thermally conductive via positioned in a region overlapping the first semiconductor chip when seen in a plan view.

22. (canceled)

23. (canceled)