METHOD AND COMPILING SYSTEM FOR GENERATING TESTBENCH FOR IC

• US 20160055272A1
• Filed: 08/24/2015
• Published: 02/25/2016
• Est. Priority Date: 08/25/2014
• Status: Abandoned Application

• Current Assignee: MediaTek Singapore Pte. Ltd. (MediaTek, Inc.)
• Original Assignee: MediaTek Singapore Pte. Ltd. (MediaTek, Inc.)
• Inventors: CHEN, Zhidong, SONG, Yunyang, HOU, Wenting
• Application Number:
  US14/833,299
• Publication Number:
  US 20160055272A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/333 Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]

Abstract

A method for generating a testbench for an IC is provided. Design information of the IC is obtained according to a bus configuration. The design information is displayed in a graphical user interface (GUI). The design information is modified according to a first user input. It is determined whether the modified design information is correct according to a register transfer level (RTL) code of the IC. The testbench for the IC is generated according to the modified design information when the modified design information is correct.

Claims

1. A method for generating a testbench for an integrated circuit (IC), comprising:

obtaining design information of the IC according to a bus configuration;

displaying the design information in a graphical user interface (GUI);

modifying the design information according to a first user input;

determining whether the modified design information is correct according to a register transfer level (RTL) code of the IC; and

generating the testbench for the IC according to the modified design information when the modified design information is correct.

2. The method as claimed in claim 1, further comprising:

displaying prompt information in the GUI when the modified design information is incorrect;

modifying the design information according to a second user input; and

generating the testbench for the IC according to the modified design information.

3. The method as claimed in claim 1, wherein the step of obtaining the design information of the IC according to the bus configuration further comprises:

obtaining a plurality of bus signals of a circuit module of the IC from the RTL code of the IC according to the bus configuration, wherein each of the bus signals has a corresponding bus capability;

classifying the bus signals according to a classification rule;

obtaining the design information according to the classified bus signals and the corresponding bus capabilities; and

storing the design information in a database.

4. The method as claimed in claim 3, wherein the classification rule is related to a naming rule of the bus signals.

5. The method as claimed in claim 3, wherein the corresponding bus capability comprises a bus width and an access direction of the corresponding bus signal.

6. The method as claimed in claim 3, wherein the design information comprises names of the bus signals and the corresponding bus capabilities.

7. The method as claimed in claim 3, wherein a user modifies the bus signals and the corresponding bus capabilities in the GUI via the first user input.

8. The method as claimed in claim 1, wherein the step of obtaining the design information of the IC according to the bus configuration further comprises:

obtaining the design information of the IC from at least one testbench for at least one of other ICs according to the bus configuration.

9. The method as claimed in claim 1, wherein the step of obtaining the design information of the IC according to the bus configuration further comprises:

obtaining design information of at least one of other ICs from a database; and

modifying the design information of the at least one of other ICs according to the bus configuration, to obtain the design information of the IC.

10. The method as claimed in claim 1, wherein the GUI is a web page.

11. The method as claimed in claim 1, wherein the step of generating the testbench for the IC according to the modified design information when the modified design information is correct further comprises:

generating an intermediary file with a specific format according to the modified design information; and

generating the testbench according to the intermediary file.

12. A compiling system for generating a testbench for an integrated circuit (IC), comprising:

a processing unit, obtaining design information of the IC according to a bus configuration;

a display unit, displaying the design information in a graphical user interface (GUI); and

a user-input unit, receiving a first user input,

wherein the processing unit modifies the design information according to a first user input, and determines whether the modified design information is correct according to a register transfer level (RTL) code of the IC,

wherein the processing unit generates the testbench for the IC according to the modified design information when the modified design information is correct.

13. The compiling system as claimed in claim 12, wherein the processing unit displays prompt information in the GUI of the display unit when the modified design information is incorrect, and the processing unit modifies the design information according to a second user input received by the user-input unit, wherein the processing unit generates the testbench for the IC according to the modified design information.

14. The compiling system as claimed in claim 12, wherein the processing unit obtains a plurality of bus signals of a circuit module of the IC from the RTL code of the IC according to the bus configuration, wherein each of the bus signals has a corresponding bus capability, and the processing unit classifies the bus signals according to a classification rule, and obtains the design information according to the classified bus signals and the corresponding bus capabilities, wherein the processing unit stores the design information in a database.

15. The compiling system as claimed in claim 14, wherein the classification rule is related to a naming rule of the bus signals.

16. The compiling system as claimed in claim 14, wherein the corresponding bus capability comprises a bus width and an access direction of the corresponding bus signal.

17. The compiling system as claimed in claim 14, wherein the design information comprises names of the bus signals and the corresponding bus capabilities.

18. The compiling system as claimed in claim 14, wherein a user modifies the bus signals and the corresponding bus capabilities in the GUI via the first user input.

19. The compiling system as claimed in claim 12, wherein the processing unit obtains the design information of the IC from at least one testbench for another IC according to the bus configuration.

20. The compiling system as claimed in claim 12, wherein the processing unit obtains design information of at least one of other ICs from a database, and modifies the design information of the at least one of other ICs according to the bus configuration, to obtain the design information of the IC.

21. The compiling system as claimed in claim 12, wherein the GUI is a web page.

22. The compiling system as claimed in claim 12, wherein the processing unit generates an intermediary file with a specific format according to the modified design information, and generates the testbench according to the intermediary file.