CHIP-STACKED SEMICONDUCTOR PACKAGE

• US 20160056101A1
• Filed: 08/05/2015
• Published: 02/25/2016
• Est. Priority Date: 08/22/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Sun-Kyoung Seo, Tae-Hong Min, Young-Kun Jee
• Inventors: JEE, Young-kun, MIN, Tae-hong, SEO, Sun-kyoung
• Granted Patent: US 9,543,276 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0346 Plating
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05138 the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05186 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05559 non conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05624 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/06181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/09517 : including bonding areas providing primarily mechanical support
• CPC Class Codes: H01L 2224/13005 : Structure
• CPC Class Codes: H01L 2224/13024 : the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13124 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1403 : Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14104 : relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/1411 : the bump connectors being bonded to at least one common bonding area
• CPC Class Codes: H01L 2224/14517 : including bump connectors providing primarily mechanical bonding
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16146 : the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16148 : the bump connector connecting to a bonding area protruding from the surface
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16238 : the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/17104 : relative to the bonding areas, e.g. bond pads
• CPC Class Codes: H01L 2224/17107 : the bump connectors connecting two common bonding areas
• CPC Class Codes: H01L 2224/17181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/17517 : including bump connectors providing primarily mechanical support
• CPC Class Codes: H01L 2224/2929 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29386 : with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/831 : the layer connector being supplied to the parts to be connected in the bonding apparatus
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/3142 : Sealing arrangements between parts, e.g. adhesion promotors
• CPC Class Codes: H01L 23/3178 : Coating or filling in grooves made in the semiconductor body
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/09 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05442 : SiO2
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A chip-stacked semiconductor package including a first chip having a plurality of first real bump pads and a plurality of first dummy bump pads, a second chip on the first chip, the second chip including a plurality of real bumps and a plurality of bridge dummy bumps, the plurality of real bumps electrically connected to the plurality of first real bump pads, the plurality of bridge dummy bumps connected to the plurality of first dummy bump pads, and a sealing member sealing the first chip and the second chip may be provided.

Claims

1. A chip-stacked semiconductor package comprising:

a first chip including a plurality of first real bump pads and a plurality of first dummy bump pads;

a second chip on the first chip, the second chip including a plurality of real bumps and a plurality of bridge dummy bumps, the plurality of real bumps electrically connected to the plurality of first real bump pads, the plurality of bridge dummy bumps connected to the plurality of first dummy bump pads; and

a sealing member sealing the first chip and the second chip.

2. The chip-stacked semiconductor package of claim 1, wherein the first chip further includes a first chip body,

the plurality of first real bump pads are on an upper surface of the first chip body, and

a plurality of first real through silicon vias are in the first chip body, and are electrically connected to the plurality of first real bump pads.

3. The chip-stacked semiconductor package of claim 2, wherein the plurality of first dummy bump pads are on the upper surface of the first chip body, and

a plurality of dummy through silicon vias are in the first chip body and are electrically connected to the plurality of first dummy bump pads.

4. The chip-stacked semiconductor package of claim 2, wherein a plurality of connection members are on a lower surface of the first chip body, the plurality of connection members are electrically connected to the plurality of first real bump pads and the plurality of first real through silicon vias.

5. The chip-stacked semiconductor package of claim 1, wherein the second chip further includes a second chip body and a plurality of second real bump pads on a lower surface of the second chip body, and

the plurality of second real bump pads are electrically connected to the plurality of real bumps.

6. The chip-stacked semiconductor package of claim 5, wherein the second chip further includes a plurality of second dummy bump pads on the lower surface thereof, the plurality of second dummy bump pads are connected to a plurality of bridge dummy bumps.

7. The chip-stacked semiconductor package of claim 5, wherein the second chip body further includes a plurality of second real through silicon vias, and the plurality of second real through silicon vias are electrically connected to the plurality of second real bump pads.

8. The chip-stacked semiconductor package of claim 6, wherein the second chip body further includes a plurality of dummy through silicon vias, and the plurality of dummy through silicon vias are connected to the plurality of second dummy bump pads.

9. The chip-stacked semiconductor package of claim 6, wherein a pitch between the plurality of first dummy bump pads and a pitch between the plurality of second dummy bump pads are smaller than a pitch between the plurality of first real bump pads and a pitch between the plurality of second real bump pads, respectively.

10. The chip-stacked semiconductor package of claim 1, wherein the plurality of bridge dummy bumps are separate from each other and the plurality of bridge dummy bumps are connected to the plurality of first dummy bump pads.

11. The chip-stacked semiconductor package of claim 1, wherein the sealing member includes an underfill, and the underfill is at least one of between the first chip and the second chip and on sides of the second chip.

12. The chip-stacked semiconductor package of claim 1, wherein the sealing member comprises a molding member, and the molding member is one of (1) between the first chip and the second chip and on sides of the first and second chips and (2) on the sides of the first and second chips and an upper surface of the second chip.

13. The chip-stacked semiconductor package of claim 1, wherein the sealing member comprises:

an underfill between the first chip and the second chip and on sides of the first chip; and

a molding member covering one of (1) the underfill and sides of the first and second chips and (2) sides of the first and second chips and an upper surface of the second chip.

14-32. -32. (canceled)

33. A chip-stacked semiconductor package comprising:

a first chip including a plurality of first real connection pads and a plurality of first dummy connection pads, the plurality of first real connection pads at a center of the first chip, the plurality of first dummy connection pads at an edge of the first chip;

a second chip on the first chip, the second chip including a plurality of second real connection pads and a plurality of second dummy connection pads, the plurality of second real connection pads at a center of the second chip, the plurality of second dummy connection pads at an edge of the second chip;

a plurality of real connection members connecting the plurality of first real connection pads and the plurality of second real connection pads;

a plurality of dummy connection members connecting the plurality of first dummy connection pads and the plurality of second dummy connection pads; and

a sealing member covering sides of the first chip and the second chip.

34. The chip-stacked semiconductor package of claim 33, wherein the plurality of dummy connection members are wider than the plurality of real connection members such that each of the dummy connection members provides a physical connection between two or more of the plurality of first dummy connection pads and corresponding two or more of the plurality of second dummy connection pads.

35. The chip-stacked semiconductor package of claim 33, wherein the first chip further includes a plurality of real through silicon vias connected to the first real connection pads.

36. The chip-stacked semiconductor package of claim 33, wherein a pitch between the plurality of first dummy connection pads and a pitch between the plurality of second dummy connection pads are smaller than a pitch between the plurality of first real connection pads and a pitch between the plurality of second real connection pads, respectively.

37. The chip-stacked semiconductor package of claim 33, wherein the sealing member is between the first chip and the second chip.

38. The chip-stacked semiconductor package of claim 33, wherein the sealing member includes an underfill and a molding member, the underfill is between the first chip and the second chip, and the molding member covers the underfill.

39. The chip-stacked semiconductor package of claim 33, wherein the sealing member includes an underfill and a molding member, the underfill is partially on at least one of sides of the first chip and sides of the second chip, and the molding member covers the underfill.