INTERCONNECT STRUCTURES FOR WAFER LEVEL PACKAGE AND METHODS OF FORMING SAME

• US 20160056126A1
• Filed: 04/14/2015
• Published: 02/25/2016
• Est. Priority Date: 08/20/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Liu, Chung-Shi
• Granted Patent: US 9,373,604 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/31051 Planarisation of the insulating layers H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/566 Release layers for moulds, e.g. release layers, layers against residue during moulding
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto when forming bonding pads H01L24/03; when forming bump connectors H01L24/11; when forming layer connectors H01L24/27
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/82031 : by chemical means, e.g. etching, anodisation
• CPC Class Codes: H01L 2224/82039 : using a laser
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1811 : Structure
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/2064 : larger or equal to 1 micron less than 100 microns

Abstract

A device package includes a plurality of dies, a molding compound extending along sidewalls of the plurality of dies, and a polymer layer over and contacting the molding compound. The molding compound comprises a non-planar top surface, and a total thickness variation (TTV) of a top surface of the polymer layer is less than a TTV of the non-planar top surface of the molding compound. The device package further includes a conductive feature on the polymer layer, wherein the conductive feature is electrically connected at least one of the plurality of dies.

Claims

1. A device package comprising:

a plurality of dies;

a molding compound extending along sidewalls of the plurality of dies, wherein the molding compound comprises a non-planar top surface;

a polymer layer over and contacting the molding compound, wherein a total thickness variation (TTV) of a top surface of the polymer layer is less than a TTV of the non-planar top surface of the molding compound; and

a conductive feature on the polymer layer, wherein the conductive feature is electrically connected at least one of the plurality of dies.

2. The device package of claim 1, wherein the non-planar top surface is disposed between adjacent ones of the plurality of dies, and wherein a portion of the polymer layer disposed on the non-planar top surface of the molding compound also comprises a non-planar top surface.

3. The device package of claim 2, wherein a TTV of the portion of the polymer layer is less than about 15 micrometers (μ

m) when a spacing between the adjacent ones of the plurality of dies is less than about 3000 μ

m.

4. The device package of claim 2, wherein a TTV of the portion of the polymer layer is less than about 10 micrometers (μ

m) when a spacing between the adjacent ones of the plurality of dies is less than about 500 μ

m.

5. The device package of claim 2, wherein a TTV of the portion of the polymer layer is less than about 5 micrometers (μ

m) when a spacing between the adjacent ones of the plurality of dies is less than about 100 μ

m.

6. The device package of claim 1, wherein the conductive feature comprises a non-planar top surface.

7. The device package of claim 1, wherein the non-planar top surface of the molding compound is concave.

8. The device package of claim 1, wherein the TTV of the non-planar top surface of the molding compound is about 5 μ

m to about 30 μ

m.

9. A device package comprising:

a first die;

a second die adjacent the first die;

a molding compound extending along sidewalls of the first die and the second die, wherein the molding compound comprises a non-planar top surface between the first die and the second die;

a polymer layer over and contacting the molding compound, wherein the polymer layer comprises a non-planar top surface over the non-planar top surface of the molding compound, and wherein the non-planar top surface of the polymer layer has a total thickness variation (TTV) less than about 5 micrometers (μ

m); and

a conductive line over the polymer layer, wherein at least a portion of the conductive line contacts the non-planar top surface of the polymer layer, and wherein the conductive line is electrically connected to the first die.

10. The device package of claim 9, wherein a TTV of the non-planar top surface of the molding compound is greater than the TTV of the non-planar top surface of the polymer layer.

11. The device package of claim 10, wherein the TTV of the molding compound is about 5 micrometers (μ

m) to about 30 μ

m.

12. The device package of claim 9, wherein a spacing between the first die and the second die is less than about 3000 μ

m.

13. The device package of claim 9, wherein the non-planar top surface of the polymer layer and the non-planar top surface of the molding compound comprise concave profiles.

14. The device package of claim 9, wherein the portion of the conductive line contacting the non-planar top surface of the polymer layer comprises a non-planar top surface.

15. The device package of claim 9 further comprising a through intervia extending through the molding compound and the polymer layer, wherein the through intervia is electrically connected to conductive elements formed over the polymer layer.

16. A method for forming device package, the method comprising:

disposing a plurality of dies on a carrier;

forming a molding compound over the carrier and around the plurality of dies, wherein the plurality of dies is covered with a film layer while forming the molding compound, and wherein the molding compound comprises a non-planar top surface between adjacent ones of the plurality of dies;

forming a polymer layer over the plurality of dies and contacting the non-planar top surface of the molding compound, wherein forming the polymer layer comprises a planarization process so that the top surface of the polymer layer has a total thickness variation (TTV) less than a TTV of the non-planar top surface of the molding compound; and

forming a conductive line on the polymer layer.

17. The method of claim 16, wherein after the planarization process the top surface of the polymer layer has a TTV less than about 5 micrometers (μ

m), and wherein a spacing between the adjacent ones of the plurality of dies is less than about 3000 μ

m.

18. The method of claim 16, wherein the planarization process comprises pressure clamping the top surface of the polymer layer.

19. The method of claim 16, wherein forming the polymer layer comprises laminating a film layer on the molding compound.

20. The method of claim 16, wherein after the planarization process, at least a portion of the polymer layer contacting the non-planar top surface of the molding compound also comprises a non-planar top surface.