Tuning Tensile Strain on FinFET
First Claim
Patent Images
1. A semiconductor device comprising:
- a first device comprising;
a first fin;
first source/drain regions in the first fin on opposing sides of a first channel region;
a first gate electrode overlying the first channel region; and
a first dielectric layer on opposing sides of the first gate electrode, the first gate electrode having substantially linear sidewalls; and
a second device comprising;
a second fin;
second source/drain regions in the second fin on opposing sides of a second channel region;
a second gate electrode overlying the second channel region; and
a second dielectric layer on opposing sides of the second gate electrode, the second gate electrode having convex sidewalls projecting toward the second dielectric layer.
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Abstract
A fin field effect transistor (FinFET) having a tunable tensile strain and an embodiment method of tuning tensile strain in an integrated circuit are provided. The method includes forming a source/drain region on opposing sides of a gate region in a fin, forming spacers over the fin, the spacers adjacent to the source/drain regions, depositing a dielectric between the spacers; and performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin.
14 Citations
20 Claims
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1. A semiconductor device comprising:
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a first device comprising; a first fin; first source/drain regions in the first fin on opposing sides of a first channel region; a first gate electrode overlying the first channel region; and a first dielectric layer on opposing sides of the first gate electrode, the first gate electrode having substantially linear sidewalls; and a second device comprising; a second fin; second source/drain regions in the second fin on opposing sides of a second channel region; a second gate electrode overlying the second channel region; and a second dielectric layer on opposing sides of the second gate electrode, the second gate electrode having convex sidewalls projecting toward the second dielectric layer. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor device comprising
a p-type metal-oxide-semiconductor (PMOS) device having a first gate electrode, first sidewalls of the first gate electrode having a first profile; - and
an n-type metal-oxide-semiconductor (NMOS) device having a second gate electrode, second sidewalls of the second gate electrode having a second profile, the first profile different than the second profile, a first channel length of the PMOS device being less than a second channel length of the NMOS device. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A semiconductor device comprising:
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a fin extending from a substrate; source/drain regions in the fin on opposing sides of a channel region; a gate over the channel region; a contracted dielectric disposed over the source/drain regions; and spacers interposed between the gate and the contracted dielectric, the spacers having a concave shape extending toward the contracted dielectric. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification